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    <title>topic Re: OTP and Shadow registers - Super Root Keys for Secure Boot in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/OTP-and-Shadow-registers-Super-Root-Keys-for-Secure-Boot/m-p/665072#M102262</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Please look at my comments below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;gt; What are Shadow Registers? Why are they used here? What happens if they &lt;BR /&gt;&amp;gt; aren't used here?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;The Shadow Registers may be considered as fuse’s cache; this allows to read and override &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;fuse values in shadow cache without affecting fuse elements.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;gt; Can I lock my device now? If I lock it will my signatures still work?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; I do not think so. The i.MX6 OTP fuses can be blown once. It is not possible to &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;restore blown bits, but is is possible to write non-blown yet bits.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note, “there is a known limitation about the verification of the SRK table in the ROM of &lt;BR /&gt;i.MX 6 Series devices. In these devices, the intent was to only verify the SRK table hash, when the &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;SRK fuse field was non-zero for Open configuration. However, for i.MX 6 Series in Open configuration, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;the HAB always skips the verification of the SRK table, regardless of whether the SRK fuse field has &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;been provisioned or not. This means that it is necessary to ensure that the SRK field is correctly programmed, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;prior to moving the i.MX 6 Series security configuration to Closed. It is highly recommended to use the srktool &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;included as part of the CST release. The byte ordering of the SRK table hash value should be correct to ensure &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;proper operation. Failing to follow the steps in provisioning the SRK hash eFuses correctly results in a device that &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;will not boot in Closed configuration."&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Also, please look at Appendix A (SRK Revocation on i.MX 6 Series) of app note&amp;nbsp; AN4581 "Secure Boot on &lt;BR /&gt;i.MX50, i.MX53, and i.MX 6 Series using HABv4", Rev. 1, 10/2015&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN&gt;&amp;lt; &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fassets%2Fdocuments%2Fdata%2Fen%2Fapplication-notes%2FAN4581.pdf" rel="nofollow" target="_blank"&gt;http://www.nxp.com/assets/documents/data/en/application-notes/AN4581.pdf&lt;/A&gt;&lt;SPAN&gt; &amp;gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;gt; Can anyone please give a logical explanation here about why these OTP &lt;BR /&gt;&amp;gt; registers rewriting works at Linux level.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;The Linux fsl_otp driver provides the function to program fuses.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;It is possible to write directly to shadow registers ; the values will not be programmed &lt;BR /&gt;to fuse if the corresponding operation flow is not performed. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct Answer &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 01 Mar 2017 07:03:00 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-03-01T07:03:00Z</dc:date>
    <item>
      <title>OTP and Shadow registers - Super Root Keys for Secure Boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/OTP-and-Shadow-registers-Super-Root-Keys-for-Secure-Boot/m-p/665071#M102261</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Everyone,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I made a strange observation and I am looking for a logical explanation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Initially, I flashed the 4SRK onto the fuse bank 3 starting from words 0 to 7 at the u-boot level using the command fuse. I signed my multi-stage bootloader and kernel and they work like a charam. I didn't lock the device yet because I want to check if the Secure Chain actually works.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Incident/Accident:&lt;/P&gt;&lt;P&gt;There is a FSL-OTP driver in Linux Kernel (not bootloader u-boot). This driver mounts the information register content onto sys. I opened the first word HW_OCOTP_SRK0 and it's available there. This is 0xD1621DC9. I edited this expecting it never change and it got saved. I was surprised it has a new value. I rebooted my device, checked it at u-boot level using the fuse command and the new value is read instead of the old one.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;=&amp;gt; fuse read 3 0 &lt;BR /&gt;Reading bank 3:&lt;/P&gt;&lt;P&gt;Word 0x00000000: dbee7fc9&lt;/P&gt;&lt;P&gt;-------------------------------------------&lt;/P&gt;&lt;P&gt;cat /sys/fsl_otp/HW_OCOTP_SRK0&lt;BR /&gt;0xdbee7fc9&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Observation:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;The Kernel and u-boot loader donot have any HAB events.&lt;/LI&gt;&lt;LI&gt;This means the original values are still saved but they are not anymore readable.&lt;/LI&gt;&lt;LI&gt;The iMX6 Reference manual talks about Shadow Registers.&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Questions:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;What are Shadow Registers? Why are they used here? What happens if they aren't used here?&lt;/LI&gt;&lt;LI&gt;Can I lock my device now? If I lock it will my signatures still work?&lt;/LI&gt;&lt;LI&gt;Can anyone please give a logical explanation here about why these OTP registers rewriting works at Linux level.&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Greets,&lt;/P&gt;&lt;P&gt;Satya&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Feb 2017 07:54:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/OTP-and-Shadow-registers-Super-Root-Keys-for-Secure-Boot/m-p/665071#M102261</guid>
      <dc:creator>satyadamarla</dc:creator>
      <dc:date>2017-02-24T07:54:38Z</dc:date>
    </item>
    <item>
      <title>Re: OTP and Shadow registers - Super Root Keys for Secure Boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/OTP-and-Shadow-registers-Super-Root-Keys-for-Secure-Boot/m-p/665072#M102262</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Please look at my comments below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;gt; What are Shadow Registers? Why are they used here? What happens if they &lt;BR /&gt;&amp;gt; aren't used here?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;The Shadow Registers may be considered as fuse’s cache; this allows to read and override &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;fuse values in shadow cache without affecting fuse elements.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;gt; Can I lock my device now? If I lock it will my signatures still work?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; I do not think so. The i.MX6 OTP fuses can be blown once. It is not possible to &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;restore blown bits, but is is possible to write non-blown yet bits.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note, “there is a known limitation about the verification of the SRK table in the ROM of &lt;BR /&gt;i.MX 6 Series devices. In these devices, the intent was to only verify the SRK table hash, when the &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;SRK fuse field was non-zero for Open configuration. However, for i.MX 6 Series in Open configuration, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;the HAB always skips the verification of the SRK table, regardless of whether the SRK fuse field has &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;been provisioned or not. This means that it is necessary to ensure that the SRK field is correctly programmed, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;prior to moving the i.MX 6 Series security configuration to Closed. It is highly recommended to use the srktool &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;included as part of the CST release. The byte ordering of the SRK table hash value should be correct to ensure &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;proper operation. Failing to follow the steps in provisioning the SRK hash eFuses correctly results in a device that &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;will not boot in Closed configuration."&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Also, please look at Appendix A (SRK Revocation on i.MX 6 Series) of app note&amp;nbsp; AN4581 "Secure Boot on &lt;BR /&gt;i.MX50, i.MX53, and i.MX 6 Series using HABv4", Rev. 1, 10/2015&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN&gt;&amp;lt; &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fassets%2Fdocuments%2Fdata%2Fen%2Fapplication-notes%2FAN4581.pdf" rel="nofollow" target="_blank"&gt;http://www.nxp.com/assets/documents/data/en/application-notes/AN4581.pdf&lt;/A&gt;&lt;SPAN&gt; &amp;gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;gt; Can anyone please give a logical explanation here about why these OTP &lt;BR /&gt;&amp;gt; registers rewriting works at Linux level.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;The Linux fsl_otp driver provides the function to program fuses.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;It is possible to write directly to shadow registers ; the values will not be programmed &lt;BR /&gt;to fuse if the corresponding operation flow is not performed. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct Answer &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Mar 2017 07:03:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/OTP-and-Shadow-registers-Super-Root-Keys-for-Secure-Boot/m-p/665072#M102262</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-03-01T07:03:00Z</dc:date>
    </item>
    <item>
      <title>Re: OTP and Shadow registers - Super Root Keys for Secure Boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/OTP-and-Shadow-registers-Super-Root-Keys-for-Secure-Boot/m-p/665073#M102263</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank for the time to reply. I have a better understanding of OTP now.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Is there a way to lock (like a hardware lock) so that no one meddle with the OTP.&amp;nbsp;&lt;/LI&gt;&lt;LI&gt;When chip security is turned on (SEC_CONFIG), can one still meddle with OTP?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Greets,&lt;/P&gt;&lt;P&gt;Satya&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Mar 2017 13:42:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/OTP-and-Shadow-registers-Super-Root-Keys-for-Secure-Boot/m-p/665073#M102263</guid>
      <dc:creator>satyadamarla</dc:creator>
      <dc:date>2017-03-06T13:42:41Z</dc:date>
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