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    <title>topic Re: Interfacing DDR3 with iMX535 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Interfacing-DDR3-with-iMX535/m-p/664636#M102137</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for the response Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Where to&amp;nbsp;obtain IBIS models for the iMX535 DDR3 @ 1.5V and 120 Ohm ODT?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What is the difference between IBIS models with ODT vs Driver impedance?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;e.g. what does driver impedance refer to? (these are the names of IBIS models for iMX535)&lt;/P&gt;&lt;P&gt;lpddr2hs_sel10_ds001_mio &amp;nbsp; &amp;nbsp; - &amp;nbsp; &amp;nbsp;DDR, 1.2V, lpddr2 mode, 240 Ohm driver impedance&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;ddr2odths_t21_sel00_mi &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;- &amp;nbsp; &amp;nbsp; DDR, 1.8V, ddr2 mode, 21 Ohm ODT&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 10 Feb 2017 17:02:07 GMT</pubDate>
    <dc:creator>sherry_zahid</dc:creator>
    <dc:date>2017-02-10T17:02:07Z</dc:date>
    <item>
      <title>Interfacing DDR3 with iMX535</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interfacing-DDR3-with-iMX535/m-p/664634#M102135</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Link me to the documents for interfacing DDR3 with iMX535. Thanks&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Feb 2017 21:43:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interfacing-DDR3-with-iMX535/m-p/664634#M102135</guid>
      <dc:creator>sherry_zahid</dc:creator>
      <dc:date>2017-02-02T21:43:16Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing DDR3 with iMX535</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interfacing-DDR3-with-iMX535/m-p/664635#M102136</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sherry&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please check i.MX53 System Development User’s Guide &lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fuser_guide%2FMX53UG.pdf" rel="nofollow" target="_blank"&gt;http://www.freescale.com/files/32bit/doc/user_guide/MX53UG.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Feb 2017 23:28:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interfacing-DDR3-with-iMX535/m-p/664635#M102136</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-02-02T23:28:34Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing DDR3 with iMX535</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interfacing-DDR3-with-iMX535/m-p/664636#M102137</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for the response Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Where to&amp;nbsp;obtain IBIS models for the iMX535 DDR3 @ 1.5V and 120 Ohm ODT?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What is the difference between IBIS models with ODT vs Driver impedance?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;e.g. what does driver impedance refer to? (these are the names of IBIS models for iMX535)&lt;/P&gt;&lt;P&gt;lpddr2hs_sel10_ds001_mio &amp;nbsp; &amp;nbsp; - &amp;nbsp; &amp;nbsp;DDR, 1.2V, lpddr2 mode, 240 Ohm driver impedance&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;ddr2odths_t21_sel00_mi &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;- &amp;nbsp; &amp;nbsp; DDR, 1.8V, ddr2 mode, 21 Ohm ODT&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 Feb 2017 17:02:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interfacing-DDR3-with-iMX535/m-p/664636#M102137</guid>
      <dc:creator>sherry_zahid</dc:creator>
      <dc:date>2017-02-10T17:02:07Z</dc:date>
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