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    <title>i.MX ProcessorsのトピックRe: NAND Implementation for IMX536</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/NAND-Implementation-for-IMX536/m-p/664181#M102028</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your help.&lt;/P&gt;&lt;P&gt;Maybe this approach can show if the system can find badblocks for my configuration of ECC. Still, this technique sounds like a partial table test, not a complete NAND test.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to find a solution without changing neither the system nor the NAND modifications I've made, because I could change the behavior of the system u&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;nintentionally and mess with the test.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;What I'm looking for is a automated solution of Laboratory Test level. This way if in the future I need to make another changes in the system, I could just ran the test again and ensure the NAND still works as I expect.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;Best Regards,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;Leonardo Ramos dos Santos&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 08 Feb 2017 10:47:19 GMT</pubDate>
    <dc:creator>leonardosantos</dc:creator>
    <dc:date>2017-02-08T10:47:19Z</dc:date>
    <item>
      <title>NAND Implementation for IMX536</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-Implementation-for-IMX536/m-p/664179#M102026</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am working on a imx53_loco based board and my last modification was to boot&amp;nbsp; the system &lt;SPAN class="" lang="en"&gt;&lt;SPAN title="Estou trabalhando em uma placa baseada em imx53_loco e minha última modificação foi para inicializar o sistema por uma memória flash NAND."&gt;through&lt;/SPAN&gt;&lt;/SPAN&gt; a NAND Flash memory. All parts of the system (hardware, bootloader, kernel and rootfs) are correctly settled-up and are working seamless (No "dmesg" prints indicating read/write errors, Read/Write from all the system components alike).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, i don't know how to ensure the system is correctly adjusted and even if it will recover bad bits and set as "bad blocks" erroneous blocks of memory.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My first thought was to change the read function in NAND driver and randomly replace a bit in the page read to force the system to recover the information. Still, it doesn't cover the write process and i don't think that's the best practice for testing NAND operation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would be glad if anyone could help by suggesting some method, hardware or software for test the NAND operation and configuration in the hole system.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Some information:&lt;/P&gt;&lt;P&gt;Based on IMX53 loco board&lt;/P&gt;&lt;P&gt;fsl-community-bsp v1.8&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Leonardo Ramos dos Santos&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Feb 2017 09:57:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-Implementation-for-IMX536/m-p/664179#M102026</guid>
      <dc:creator>leonardosantos</dc:creator>
      <dc:date>2017-02-02T09:57:13Z</dc:date>
    </item>
    <item>
      <title>Re: NAND Implementation for IMX536</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-Implementation-for-IMX536/m-p/664180#M102027</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Leonardo&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;seems one can generate image for less ecc level than required and check it.&lt;/P&gt;&lt;P&gt;For example for 16 bit ecc nand generate 8 bit ecc image (BOOT_CFG3[4:3],&lt;/P&gt;&lt;P&gt;Table 7-11. NAND Boot eFUSE Descriptions).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Feb 2017 23:21:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-Implementation-for-IMX536/m-p/664180#M102027</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-02-02T23:21:19Z</dc:date>
    </item>
    <item>
      <title>Re: NAND Implementation for IMX536</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NAND-Implementation-for-IMX536/m-p/664181#M102028</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your help.&lt;/P&gt;&lt;P&gt;Maybe this approach can show if the system can find badblocks for my configuration of ECC. Still, this technique sounds like a partial table test, not a complete NAND test.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to find a solution without changing neither the system nor the NAND modifications I've made, because I could change the behavior of the system u&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;nintentionally and mess with the test.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;What I'm looking for is a automated solution of Laboratory Test level. This way if in the future I need to make another changes in the system, I could just ran the test again and ensure the NAND still works as I expect.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;Best Regards,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class=""&gt;Leonardo Ramos dos Santos&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Feb 2017 10:47:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NAND-Implementation-for-IMX536/m-p/664181#M102028</guid>
      <dc:creator>leonardosantos</dc:creator>
      <dc:date>2017-02-08T10:47:19Z</dc:date>
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