PF0200 - OTP Version Solo compatibility

max123 — Thu, 29 Sep 2016 14:24:21 GMT

Hi,

i want to supply a i.MX6-Solo-Design with DDR3L using a PF0200.

As far as i understand the power-up process (datasheet 4.2.1) i need to apply the VDD_SNVS_IN / VDD_HIGH_IN (which are connected in my design) first and can then power up the other supplys in any order.

So i think i may be able to use the F6 - OTP-Variant of the PF0200, if i connect:

- VGEN6_VOLT for VDD_SNVS_IN / VDD_HIGH_IN (which is powered first)

- SW1 for core voltages (ARM; SOC) (order : 2)

- SW3 for Memory (order : 3)

- SW2 for IOs (order : 4)

Is that correct?

Are there recommendation, which OTP-variant is suitable for which processor?

Re: PF0200 - OTP Version Solo compatibility

igorpadykov — Thu, 29 Sep 2016 23:47:38 GMT

Hi Maximilian

one can look at Table 1. Orderable Part Variations MMPF0200 Datasheet
http://cache.freescale.com/files/analog/doc/data_sheet/MMPF0200.pdf
MMPF0200F6 is used on i.MX6SX SabreSD board
Schematics (1)
IMX6SOLOX-SABRESDB-DESIGNFILES
http://www.nxp.com/products/software-and-tools/hardware-development-tools/sabre-development-system/sabre-board-for-smart-devices-based-on-the-i.mx-6solox-applications-processors:RD-IMX6SX-SABRE?fpsp=1&tab=Design_Tools_Tab

Best regards
igor
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i.MX ProcessorsのトピックRe: PF0200 - OTP Version Solo compatibility

PF0200 - OTP Version Solo compatibility

Re: PF0200 - OTP Version Solo compatibility