<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: IMX6Q UART Interrupt in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663671#M101930</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Oh, glad to hear that the problem is resolved :-)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 27 Oct 2016 12:20:14 GMT</pubDate>
    <dc:creator>art</dc:creator>
    <dc:date>2016-10-27T12:20:14Z</dc:date>
    <item>
      <title>IMX6Q UART Interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663668#M101927</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;BR /&gt;I am using I.MX6Q Sabre sd board. I am trying to build custom image with my own start script and ld script. The image is to be loaded with u-boot. I am trying to enable the UART receive interrupt for UART1. But it does not enter the Interrupt service routine. I am able to sent and recieve data by polling. What is the basic initialisation step for enabling uart interrupt? I have initialised the uart as follows,&lt;/P&gt;&lt;P&gt;void UART1_init(void)&lt;BR /&gt;{&lt;BR /&gt;int tmp;&lt;BR /&gt;//*********** UART1 IOMUX****************//&lt;BR /&gt;* R32 (IOMUXC_BASE_ADDR+0x280) = 0x00000003; // ALT3 CSI0_DAT10 TxD&lt;BR /&gt;* R32 (IOMUXC_BASE_ADDR+0x284) = 0x00000003; // ALT3 CSI0_DAT11 RxD&lt;BR /&gt;* R32 (IOMUXC_BASE_ADDR+0x920) = 0x00000001; //UART1_UART_RX_DATA_SELECT_INPUT&lt;BR /&gt;tmp=(* R32 (CCM_BASE_ADDR+0x24)) &amp;amp; 0x0000003F ; //CSCDR1 uart_podf div by 1&lt;BR /&gt;* R32 (CCM_BASE_ADDR+0x24) = tmp; // UART refclk = 80MHz&lt;BR /&gt; &lt;BR /&gt;// Enable UART1&lt;BR /&gt;// enable uart1, ignore RTS, wordsize 8bits, 1 stop bit, no parity&lt;BR /&gt;*(unsigned int*)(UART1_UCR2_1) = 0x01; // reset UART state machines &lt;BR /&gt;*(unsigned int*)(UART1_UCR2_1) = 0x2006; // UCR2 = CTSC,TXEN,RXEN=1,reset&lt;BR /&gt;*(unsigned int*)(UART1_UCR1_1) = 0x0001; // UARTEN = 1,enable the clock&lt;BR /&gt;*(unsigned int*)(UART1_UCR2_1) |= IGNORE_RTS&amp;lt;&amp;lt;14; // configure IRTS bit&lt;BR /&gt;*(unsigned int*)(UART1_UCR2_1) |= WORD8&amp;lt;&amp;lt;5;&lt;BR /&gt;*(unsigned int*)(UART1_UCR2_1) |= STOP1&amp;lt;&amp;lt;6;&lt;BR /&gt;*(unsigned int*)(UART1_UCR3_1) |= 0x00000004; // set RXD_MUX_SEL bit&lt;BR /&gt;*(unsigned int*)(UART1_UCR1_1) |= 0x0201; // recieve ready interput enable&lt;/P&gt;&lt;P&gt;// disable parity&lt;BR /&gt;*(unsigned int*)(UART1_UCR2_1) &amp;amp;= ~(0x00000100);&lt;/P&gt;&lt;P&gt;//SetRFDIV_to_div_by_1_UART1(); &lt;BR /&gt;tmp = *(unsigned int*)(UART1_UFCR_1); // save UFCR to default value&lt;BR /&gt;*(unsigned int*)(UART1_UFCR_1) = 5&amp;lt;&amp;lt;7; // set RFDIV to div-by-1 or b101 &lt;BR /&gt;*(unsigned int*)(UART1_UFCR_1) |= tmp; // set other UFCR bits back to default&lt;BR /&gt;*(unsigned int*)(UART1_UBIR_1) = 0x4;&lt;BR /&gt;*(unsigned int*)(UART1_UBMR_1) = 0xD8;&lt;BR /&gt;*(unsigned int*)(UART1_UCR3_1) |= 0x00000040; &lt;BR /&gt;*(unsigned int*)(UART1_UCR4_1) |= 0x00000081; &lt;BR /&gt; &lt;BR /&gt;/* RxTl =1 */&lt;BR /&gt;tmp = *(unsigned int*)(UART1_UFCR_1);&lt;BR /&gt;tmp = tmp &amp;amp; 0xffffffc0;&lt;BR /&gt;tmp = tmp | 0x00000001;&lt;BR /&gt;*(unsigned int*)(UART1_UFCR_1) = tmp;&lt;BR /&gt; &lt;BR /&gt;/* Rf div */&lt;BR /&gt;tmp = *(unsigned int*)(UART1_UCR1_1);&lt;BR /&gt;tmp = tmp &amp;amp; 0xfffffcff;&lt;BR /&gt;tmp = tmp | 0x00000200;&lt;BR /&gt;*(unsigned int*)(UART1_UCR1_1) = tmp;&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;Am i missing some initialization steps for uart receive interrupt?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Oct 2016 06:04:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663668#M101927</guid>
      <dc:creator>ajmalali</dc:creator>
      <dc:date>2016-10-24T06:04:46Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q UART Interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663669#M101928</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #242729; background-color: #ffffff;"&gt;I found the problem. It wasn't in the UART initialization. I forgot to set the VBAR register(vector base address register), whose reset value is 0x00000000. I had linked my vector table at 0x0093ff80. After correctly setting the VBAR register, the UART interrupt is working fine with the above initializations. This is how i set VBAR,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;PRE style="background-color: #eff0f1; border: 0px; font-size: 13px; margin: 0px 0px 1em; padding: 5px;"&gt;&lt;CODE style="background-color: #eff0f1; border: 0px; font-size: 13px;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;ldr r6,=__ram_vectors_start
&amp;nbsp;&amp;nbsp;&amp;nbsp;MCR p15,0,r6,c12,c0,0
&amp;nbsp;&amp;nbsp;&amp;nbsp;MCR p15,0,r6,c12,c0,1

Regards,
Ajmal&lt;/CODE&gt;&lt;/PRE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Oct 2016 09:05:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663669#M101928</guid>
      <dc:creator>ajmalali</dc:creator>
      <dc:date>2016-10-27T09:05:57Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q UART Interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663670#M101929</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Have you properly initialized your UART interrupt handling routine and linked it to the correct interrupt vector? Please check.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Oct 2016 12:19:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663670#M101929</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-10-27T12:19:10Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q UART Interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663671#M101930</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Oh, glad to hear that the problem is resolved :-)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Oct 2016 12:20:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-UART-Interrupt/m-p/663671#M101930</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-10-27T12:20:14Z</dc:date>
    </item>
  </channel>
</rss>

