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    <title>i.MX Processors中的主题 Re: Mipi OLED interface errors after interfacing</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Mipi-OLED-interface-errors-after-interfacing/m-p/662438#M101701</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Kunal&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please check attached Linux Manual Chapter 7 MIPI DSI Driver.&lt;/P&gt;&lt;P&gt;For 400x400 resolution fb_videomode truly_lcd_modedb[], mxcfb_hx8369_wvga.c&lt;/P&gt;&lt;P&gt;should be customized with new panel timings. Also&amp;nbsp;manufacturer init code&lt;/P&gt;&lt;P&gt;should be placed in mipid_hx8369_lcd_setup().&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 10 Apr 2017 23:35:39 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-04-10T23:35:39Z</dc:date>
    <item>
      <title>Mipi OLED interface errors after interfacing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Mipi-OLED-interface-errors-after-interfacing/m-p/662437#M101700</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Team,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I need help while I try to interface a 400x400 round OLED to iMX6. Attaching the logs and datasheet. Please let me know the points which could be wrong.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have attached the mxcfb_hx8369_wvga.c which I am using and the Init code file which I have received from manufacturer. I also am looking forward to know if the lcd_setup function in mxcfb_hx8369_wvga.c looks ok. How to I write the data to registers as is expected in the pdf of init code?&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any help will be great.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;amp;mipi_dsi {&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;compatible = "fsl,imx6dl-mipi-dsi";&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;reg = &amp;lt;0x021e0000 0x4000&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;interrupts = &amp;lt;0 102 0x04&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;gpr = &amp;lt;&amp;amp;gpr&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;clocks = &amp;lt;&amp;amp;clks 138&amp;gt;, &amp;lt;&amp;amp;clks 204&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;clock-names = "mipi_pllref_clk", "mipi_cfg_clk";&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;dev_id = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;disp_id = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;lcd_panel = "TRULY-WVGA";&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;disp-power-on-supply = &amp;lt;&amp;amp;reg_mipi_dsi_pwr_on&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;resets = &amp;lt;&amp;amp;mipi_dsi_reset&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; mipi_dsi_reset: mipi-dsi-reset {&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;compatible = "gpio-reset";&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reset-gpios = &amp;lt;&amp;amp;gpio5 15 GPIO_ACTIVE_LOW&amp;gt;; &lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reset-delay-us = &amp;lt;50&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;#reset-cells = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;};&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;compatible = "regulator-fixed";&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;regulator-name = "mipi_dsi_pwr_on";&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;gpio = &amp;lt;&amp;amp;gpio6 14 0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;enable-active-high;&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;};&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;U-Boot 2014.04 (Jan 04 2017 - 21:04:41)&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;CPU:&amp;nbsp;&amp;nbsp; Freescale i.MX6DL rev1.2 at 792 MHz&lt;BR /&gt;Reset cause: POR&lt;BR /&gt;Board: MX6-Sabreauto revA&lt;BR /&gt;I2C:&amp;nbsp;&amp;nbsp; ready&lt;BR /&gt;DRAM:&amp;nbsp; 2 GiB&lt;BR /&gt;NAND:&amp;nbsp; 0 MiB&lt;BR /&gt;MMC:&amp;nbsp;&amp;nbsp; FSL_SDHC: 0, FSL_SDHC: 1&lt;BR /&gt;No panel detected: default to Hannstar-XGA&lt;BR /&gt;Display: Hannstar-XGA (1024x768)&lt;BR /&gt;In:&amp;nbsp;&amp;nbsp;&amp;nbsp; serial&lt;BR /&gt;Out:&amp;nbsp;&amp;nbsp; serial&lt;BR /&gt;Err:&amp;nbsp;&amp;nbsp; serial&lt;BR /&gt;Found PFUZE100! deviceid=10,revid=12&lt;BR /&gt;mmc1 is current device&lt;BR /&gt;Net:&amp;nbsp;&amp;nbsp; FEC [PRIME]&lt;BR /&gt;Normal Boot&lt;BR /&gt;Hit any key to stop autoboot:&amp;nbsp; 0 &lt;BR /&gt;mmc1 is current device&lt;BR /&gt;reading boot.scr&lt;BR /&gt;** Unable to read file boot.scr **&lt;BR /&gt;reading zImage&lt;BR /&gt;5933744 bytes read in 276 ms (20.5 MiB/s)&lt;BR /&gt;Booting from mmc ...&lt;BR /&gt;reading imx6dl-sabreauto.dtb&lt;BR /&gt;43719 bytes read in 19 ms (2.2 MiB/s)&lt;BR /&gt;Kernel image @ 0x12000000 [ 0x000000 - 0x5a8ab0 ]&lt;BR /&gt;## Flattened Device Tree blob at 18000000&lt;BR /&gt;&amp;nbsp;&amp;nbsp; Booting using the fdt blob at 0x18000000&lt;BR /&gt;&amp;nbsp;&amp;nbsp; Using Device Tree in place at 18000000, end 1800dac6&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Starting kernel ...&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Booting Linux on physical CPU 0x0&lt;BR /&gt;Linux version 3.14.28-1.0.0_ga+g91cf351 (kunalk@Linux2-tds) (gcc version 4.9.1 (GCC) ) #21 SMP PREEMPT Mon Apr 10 19:49:36 IST 2017&lt;BR /&gt;CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d&lt;BR /&gt;CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache&lt;BR /&gt;Machine model: Freescale i.MX6 DualLite/Solo SABRE Automotive Board&lt;BR /&gt;cma: CMA: reserved 320 MiB at 6a000000&lt;BR /&gt;Memory policy: Data cache writealloc&lt;BR /&gt;PERCPU: Embedded 8 pages/cpu @ee72d000 s8896 r8192 d15680 u32768&lt;BR /&gt;Built 1 zonelists in Zone order, mobility grouping on.&amp;nbsp; Total pages: 520720&lt;BR /&gt;Kernel command line: console=ttymxc3,115200 root=/dev/mmcblk2p2 rootwait rw&lt;BR /&gt;PID hash table entries: 4096 (order: 2, 16384 bytes)&lt;BR /&gt;Dentry cache hash table entries: 262144 (order: 8, 1048576 bytes)&lt;BR /&gt;Inode-cache hash table entries: 131072 (order: 7, 524288 bytes)&lt;BR /&gt;Memory: 1736120K/2097152K available (7217K kernel code, 394K rwdata, 6144K rodata, 328K init, 428K bss, 361032K reserved, 270336K highmem)&lt;BR /&gt;Virtual kernel memory layout:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; vector&amp;nbsp; : 0xffff0000 - 0xffff1000&amp;nbsp;&amp;nbsp; (&amp;nbsp;&amp;nbsp; 4 kB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; fixmap&amp;nbsp; : 0xfff00000 - 0xfffe0000&amp;nbsp;&amp;nbsp; ( 896 kB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; vmalloc : 0xf0000000 - 0xff000000&amp;nbsp;&amp;nbsp; ( 240 MB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; lowmem&amp;nbsp; : 0x80000000 - 0xef800000&amp;nbsp;&amp;nbsp; (1784 MB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; pkmap&amp;nbsp;&amp;nbsp; : 0x7fe00000 - 0x80000000&amp;nbsp;&amp;nbsp; (&amp;nbsp;&amp;nbsp; 2 MB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; modules : 0x7f000000 - 0x7fe00000&amp;nbsp;&amp;nbsp; (&amp;nbsp; 14 MB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .text : 0x80008000 - 0x80d146c4&amp;nbsp;&amp;nbsp; (13362 kB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .init : 0x80d15000 - 0x80d672c0&amp;nbsp;&amp;nbsp; ( 329 kB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .data : 0x80d68000 - 0x80dcab40&amp;nbsp;&amp;nbsp; ( 395 kB)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .bss : 0x80dcab4c - 0x80e35e1c&amp;nbsp;&amp;nbsp; ( 429 kB)&lt;BR /&gt;SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1&lt;BR /&gt;Preemptible hierarchical RCU implementation.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.&lt;BR /&gt;RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2&lt;BR /&gt;NR_IRQS:16 nr_irqs:16 16&lt;BR /&gt;L310 cache controller enabled&lt;BR /&gt;l2x0: 16 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x32050000, Cache size: 512 kB&lt;BR /&gt;failed to set parent of clk gpu2d_core_sel to pll2_pfd1_594m: -22&lt;BR /&gt;Switching to timer-based delay loop&lt;BR /&gt;sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655765682ns&lt;BR /&gt;Console: colour dummy device 80x30&lt;BR /&gt;Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=30000)&lt;BR /&gt;pid_max: default: 32768 minimum: 301&lt;BR /&gt;Mount-cache hash table entries: 4096 (order: 2, 16384 bytes)&lt;BR /&gt;Mountpoint-cache hash table entries: 4096 (order: 2, 16384 bytes)&lt;BR /&gt;CPU: Testing write buffer coherency: ok&lt;BR /&gt;CPU0: thread -1, cpu 0, socket 0, mpidr 80000000&lt;BR /&gt;Setting up static identity map for 0x106de8e0 - 0x106de938&lt;BR /&gt;CPU1: Booted secondary processor&lt;BR /&gt;CPU1: thread -1, cpu 1, socket 0, mpidr 80000001&lt;BR /&gt;Brought up 2 CPUs&lt;BR /&gt;SMP: Total of 2 processors activated.&lt;BR /&gt;CPU: All CPU(s) started in SVC mode.&lt;BR /&gt;devtmpfs: initialized&lt;BR /&gt;VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4&lt;BR /&gt;pinctrl core: initialized pinctrl subsystem&lt;BR /&gt;regulator-dummy: no parameters&lt;BR /&gt;NET: Registered protocol family 16&lt;BR /&gt;DMA: preallocated 256 KiB pool for atomic coherent allocations&lt;BR /&gt;cpuidle: using governor ladder&lt;BR /&gt;cpuidle: using governor menu&lt;BR /&gt;CPU identified as i.MX6DL, silicon rev 1.2&lt;BR /&gt;Use WDOG1 as reset source&lt;BR /&gt;syscon 20c8000.anatop: regmap [mem 0x020c8000-0x020c8fff] registered&lt;BR /&gt;vdd1p1: 800 &amp;lt;--&amp;gt; 1375 mV at 1100 mV &lt;BR /&gt;vdd3p0: 2800 &amp;lt;--&amp;gt; 3150 mV at 3000 mV &lt;BR /&gt;vdd2p5: 2000 &amp;lt;--&amp;gt; 2750 mV at 2400 mV &lt;BR /&gt;vddarm: 725 &amp;lt;--&amp;gt; 1450 mV at 1150 mV &lt;BR /&gt;vddpu: 725 &amp;lt;--&amp;gt; 1450 mV &lt;BR /&gt;vddsoc: 725 &amp;lt;--&amp;gt; 1450 mV at 1175 mV &lt;BR /&gt;syscon 20e0000.iomuxc-gpr: regmap [mem 0x020e0000-0x020e0037] registered&lt;BR /&gt;syscon 21bc000.ocotp-ctrl: regmap [mem 0x021bc000-0x021bffff] registered&lt;BR /&gt;hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.&lt;BR /&gt;hw-breakpoint: maximum watchpoint size is 4 bytes.&lt;BR /&gt;imx6dl-pinctrl 20e0000.iomuxc: Invalid fsl,pins property in node /soc/aips-bus@02000000/iomuxc@020e0000/imx6qdl-sabreauto/audmux&lt;BR /&gt;imx6dl-pinctrl 20e0000.iomuxc: initialized IMX pinctrl driver&lt;BR /&gt;bio: create slab &amp;lt;bio-0&amp;gt; at 0&lt;BR /&gt;mxs-dma 110000.dma-apbh: initialized&lt;BR /&gt;cs42888_supply: 3300 mV &lt;BR /&gt;3P3V: 3300 mV &lt;BR /&gt;vio1: 3300 mV &lt;BR /&gt;vio2: 3300 mV &lt;BR /&gt;vd: 3300 mV &lt;BR /&gt;va: 5000 mV &lt;BR /&gt;platform usb_h1_vbus.28: Driver reg-fixed-voltage requests probe deferral&lt;BR /&gt;platform usb_otg_vbus.29: Driver reg-fixed-voltage requests probe deferral&lt;BR /&gt;mipi_dsi_pwr_on: no parameters&lt;BR /&gt;i2c-core: driver [max17135] using legacy suspend method&lt;BR /&gt;i2c-core: driver [max17135] using legacy resume method&lt;BR /&gt;SCSI subsystem initialized&lt;BR /&gt;usbcore: registered new interface driver usbfs&lt;BR /&gt;usbcore: registered new interface driver hub&lt;BR /&gt;usbcore: registered new device driver usb&lt;BR /&gt;usbphy_nop1.12 supply vcc not found, using dummy regulator&lt;BR /&gt;usbphy_nop2.13 supply vcc not found, using dummy regulator&lt;BR /&gt;i2c i2c-1: IMX I2C adapter registered&lt;BR /&gt;i2c i2c-2: IMX I2C adapter registered&lt;BR /&gt;Linux video capture interface: v2.00&lt;BR /&gt;pps_core: LinuxPPS API ver. 1 registered&lt;BR /&gt;&lt;SPAN&gt;pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:giometti@linux.it"&gt;giometti@linux.it&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;PTP clock support registered&lt;BR /&gt;imx-ipuv3 2400000.ipu: IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)&lt;BR /&gt;MIPI CSI2 driver module loaded&lt;BR /&gt;Advanced Linux Sound Architecture Driver Initialized.&lt;BR /&gt;Bluetooth: Core ver 2.18&lt;BR /&gt;NET: Registered protocol family 31&lt;BR /&gt;Bluetooth: HCI device and connection manager initialized&lt;BR /&gt;Bluetooth: HCI socket layer initialized&lt;BR /&gt;Bluetooth: L2CAP socket layer initialized&lt;BR /&gt;Bluetooth: SCO socket layer initialized&lt;BR /&gt;cfg80211: Calling CRDA to update world regulatory domain&lt;BR /&gt;Switched to clocksource mxc_timer1&lt;BR /&gt;NET: Registered protocol family 2&lt;BR /&gt;TCP established hash table entries: 16384 (order: 4, 65536 bytes)&lt;BR /&gt;TCP bind hash table entries: 16384 (order: 5, 131072 bytes)&lt;BR /&gt;TCP: Hash tables configured (established 16384 bind 16384)&lt;BR /&gt;TCP: reno registered&lt;BR /&gt;UDP hash table entries: 1024 (order: 3, 32768 bytes)&lt;BR /&gt;UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)&lt;BR /&gt;NET: Registered protocol family 1&lt;BR /&gt;RPC: Registered named UNIX socket transport module.&lt;BR /&gt;RPC: Registered udp transport module.&lt;BR /&gt;RPC: Registered tcp transport module.&lt;BR /&gt;RPC: Registered tcp NFSv4.1 backchannel transport module.&lt;BR /&gt;hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available&lt;BR /&gt;Bus freq driver module loaded&lt;BR /&gt;futex hash table entries: 512 (order: 3, 32768 bytes)&lt;BR /&gt;bounce pool size: 64 pages&lt;BR /&gt;VFS: Disk quotas dquot_6.5.2&lt;BR /&gt;Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)&lt;BR /&gt;NFS: Registering the id_resolver key type&lt;BR /&gt;Key type id_resolver registered&lt;BR /&gt;Key type id_legacy registered&lt;BR /&gt;jffs2: version 2.2. (NAND) ������ 2001-2006 Red Hat, Inc.&lt;BR /&gt;fuse init (API version 7.22)&lt;BR /&gt;msgmni has been set to 3502&lt;BR /&gt;io scheduler noop registered&lt;BR /&gt;io scheduler deadline registered&lt;BR /&gt;io scheduler cfq registered (default)&lt;BR /&gt;backlight.17 supply power not found, using dummy regulator&lt;BR /&gt;ldb ldb.15: crtc not specified or invalid&lt;BR /&gt;ldb: probe of ldb.15 failed with error -22&lt;BR /&gt;Before Device Reset&lt;BR /&gt;After Device Reset ret = 0&lt;BR /&gt;mipi_dsi 21e0000.mipi: i.MX MIPI DSI driver probed&lt;BR /&gt;MIPI DSI driver module loaded&lt;BR /&gt;imx6dl-pinctrl 20e0000.iomuxc: pin MX6DL_PAD_DISP0_DAT21 already requested by 20e0000.iomuxc; cannot claim for lcd.24&lt;BR /&gt;imx6dl-pinctrl 20e0000.iomuxc: pin-58 (lcd.24) status -22&lt;BR /&gt;imx6dl-pinctrl 20e0000.iomuxc: could not request pin 58 (MX6DL_PAD_DISP0_DAT21) from group ipu1grp-1&amp;nbsp; on device 20e0000.iomuxc&lt;BR /&gt;mxc_lcdif lcd.24: Error applying setting, reverse things back&lt;BR /&gt;imx6dl-pinctrl 20e0000.iomuxc: pin MX6DL_PAD_DISP0_DAT21 already requested by 20e0000.iomuxc; cannot claim for lcd.24&lt;BR /&gt;imx6dl-pinctrl 20e0000.iomuxc: pin-58 (lcd.24) status -22&lt;BR /&gt;imx6dl-pinctrl 20e0000.iomuxc: could not request pin 58 (MX6DL_PAD_DISP0_DAT21) from group ipu1grp-1&amp;nbsp; on device 20e0000.iomuxc&lt;BR /&gt;mxc_lcdif lcd.24: Error applying setting, reverse things back&lt;BR /&gt;mxc_lcdif lcd.24: can't get/select pinctrl&lt;BR /&gt;mxc_lcdif: probe of lcd.24 failed with error -22&lt;BR /&gt;mxc_sdc_fb fb.23: registered mxc display driver mipi_dsi&lt;BR /&gt;Console: switching to colour frame buffer device 50x25&lt;BR /&gt;imx_epdc_fb 20f4000.epdc: can't get/select pinctrl&lt;BR /&gt;imx-sdma 20ec000.sdma: no iram assigned, using external mem&lt;BR /&gt;imx-sdma 20ec000.sdma: no event needs to be remapped&lt;BR /&gt;imx-sdma 20ec000.sdma: loaded firmware 3.1&lt;BR /&gt;imx-sdma 20ec000.sdma: initialized&lt;BR /&gt;pfuze100-regulator 1-0008: Full layer: 1, Metal layer: 2&lt;BR /&gt;pfuze100-regulator 1-0008: FAB: 0, FIN: 0&lt;BR /&gt;pfuze100-regulator 1-0008: pfuze100 found.&lt;BR /&gt;SW1AB: 300 &amp;lt;--&amp;gt; 1875 mV at 1375 mV &lt;BR /&gt;SW1C: 300 &amp;lt;--&amp;gt; 1875 mV at 1375 mV &lt;BR /&gt;SW2: 800 &amp;lt;--&amp;gt; 3300 mV at 3000 mV &lt;BR /&gt;SW3A: 400 &amp;lt;--&amp;gt; 1975 mV at 1500 mV &lt;BR /&gt;SW3B: 400 &amp;lt;--&amp;gt; 1975 mV at 1500 mV &lt;BR /&gt;SW4: 800 &amp;lt;--&amp;gt; 1975 mV at 1800 mV &lt;BR /&gt;SWBST: 5000 &amp;lt;--&amp;gt; 5150 mV at 5000 mV &lt;BR /&gt;VSNVS: 1000 &amp;lt;--&amp;gt; 3000 mV at 3000 mV &lt;BR /&gt;VREFDDR: 750 mV &lt;BR /&gt;VGEN1: 800 &amp;lt;--&amp;gt; 1550 mV at 800 mV &lt;BR /&gt;VGEN2: 800 &amp;lt;--&amp;gt; 1550 mV at 1500 mV &lt;BR /&gt;VGEN3: 1800 &amp;lt;--&amp;gt; 3300 mV at 1800 mV &lt;BR /&gt;VGEN4: 1800 &amp;lt;--&amp;gt; 3300 mV at 1800 mV &lt;BR /&gt;VGEN5: 1800 &amp;lt;--&amp;gt; 3300 mV at 2500 mV &lt;BR /&gt;VGEN6: 1800 &amp;lt;--&amp;gt; 3300 mV at 2800 mV &lt;BR /&gt;Serial: IMX driver&lt;BR /&gt;21e8000.serial: ttymxc1 at MMIO 0x21e8000 (irq = 59, base_baud = 5000000) is a IMX&lt;BR /&gt;21ec000.serial: ttymxc2 at MMIO 0x21ec000 (irq = 60, base_baud = 5000000) is a IMX&lt;BR /&gt;21f0000.serial: ttymxc3 at MMIO 0x21f0000 (irq = 61, base_baud = 5000000) is a IMX&lt;BR /&gt;console [ttymxc3] enabled&lt;BR /&gt;serial: Freescale lpuart driver&lt;BR /&gt;imx sema4 driver is registered.&lt;BR /&gt;[drm] Initialized drm 1.1.0 20060810&lt;BR /&gt;[drm] Initialized vivante 1.0.0 20120216 on minor 0&lt;BR /&gt;brd: module loaded&lt;BR /&gt;loop: module loaded&lt;BR /&gt;si476x-core 1-0063: Using default platform data.&lt;BR /&gt;si476x-core 1-0063: No IRQ number specified, will use polling&lt;BR /&gt;si476x-core 1-0063: Error while sending command 0x11&lt;BR /&gt;si476x-core 1-0063: The device in inconsistent power state&lt;BR /&gt;CAN device driver interface&lt;BR /&gt;2094000.can supply xceiver not found, using dummy regulator&lt;BR /&gt;flexcan 2094000.can: device registered (reg_base=f01c0000, irq=143)&lt;BR /&gt;2188000.ethernet supply phy not found, using dummy regulator&lt;BR /&gt;pps pps0: new PPS source ptp0&lt;BR /&gt;libphy: fec_enet_mii_bus: probed&lt;BR /&gt;fec 2188000.ethernet eth0: registered PHC device 0&lt;BR /&gt;ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver&lt;BR /&gt;ehci-mxc: Freescale On-Chip EHCI Host driver&lt;BR /&gt;usbcore: registered new interface driver usb-storage&lt;BR /&gt;2184800.usbmisc supply vbus-wakeup not found, using dummy regulator&lt;BR /&gt;imx_usb 2184000.usb: Can't register ci_hdrc platform device, err=-517&lt;BR /&gt;platform 2184000.usb: Driver imx_usb requests probe deferral&lt;BR /&gt;imx_usb 2184200.usb: Can't register ci_hdrc platform device, err=-517&lt;BR /&gt;platform 2184200.usb: Driver imx_usb requests probe deferral&lt;BR /&gt;mousedev: PS/2 mouse device common for all mice&lt;BR /&gt;egalax_ts 1-0004: Failed to read firmware version&lt;BR /&gt;egalax_ts: probe of 1-0004 failed with error -5&lt;BR /&gt;2-0044 supply vdd not found, using dummy regulator&lt;BR /&gt;i2c-core: driver [isl29023] using legacy suspend method&lt;BR /&gt;i2c-core: driver [isl29023] using legacy resume method&lt;BR /&gt;snvs_rtc 20cc034.snvs-rtc-lp: rtc core: registered 20cc034.snvs-rtc-lp as rtc0&lt;BR /&gt;i2c /dev entries driver&lt;BR /&gt;IR NEC protocol handler initialized&lt;BR /&gt;IR RC5(x) protocol handler initialized&lt;BR /&gt;IR RC6 protocol handler initialized&lt;BR /&gt;IR JVC protocol handler initialized&lt;BR /&gt;IR Sony protocol handler initialized&lt;BR /&gt;IR RC5 (streamzap) protocol handler initialized&lt;BR /&gt;IR SANYO protocol handler initialized&lt;BR /&gt;IR MCE Keyboard/mouse protocol handler initialized&lt;BR /&gt;mxc_v4l2_output v4l2_out.32: V4L2 device registered as video16&lt;BR /&gt;mxc_v4l2_output v4l2_out.32: V4L2 device registered as video17&lt;BR /&gt;2-000e supply vdd not found, using dummy regulator&lt;BR /&gt;2-000e supply vddio not found, using dummy regulator&lt;BR /&gt;mag3110 2-000e: check mag3110 chip ID&lt;BR /&gt;mag3110 2-000e: read chip ID 0xfffffffb is not equal to 0xc4!&lt;BR /&gt;mag3110: probe of 2-000e failed with error -22&lt;BR /&gt;i2c-core: driver [mag3110] using legacy suspend method&lt;BR /&gt;i2c-core: driver [mag3110] using legacy resume method&lt;BR /&gt;2-001c supply vdd not found, using dummy regulator&lt;BR /&gt;2-001c supply vddio not found, using dummy regulator&lt;BR /&gt;mma8451 2-001c: read chip ID 0x1 is not equal to 0x1a or 0x2a!&lt;BR /&gt;mma8451: probe of 2-001c failed with error -22&lt;BR /&gt;imx2-wdt 20bc000.wdog: IMX2+ Watchdog Timer enabled. timeout=60s (nowayout=0)&lt;BR /&gt;Bluetooth: HCI UART driver ver 2.2&lt;BR /&gt;Bluetooth: HCI H4 protocol initialized&lt;BR /&gt;Bluetooth: HCI BCSP protocol initialized&lt;BR /&gt;Bluetooth: HCIATH3K protocol initialized&lt;BR /&gt;usbcore: registered new interface driver bcm203x&lt;BR /&gt;usbcore: registered new interface driver btusb&lt;BR /&gt;Bluetooth: Generic Bluetooth SDIO driver ver 0.1&lt;BR /&gt;usbcore: registered new interface driver ath3k&lt;BR /&gt;sdhci: Secure Digital Host Controller Interface driver&lt;BR /&gt;sdhci: Copyright(c) Pierre Ossman&lt;BR /&gt;sdhci-pltfm: SDHCI platform and OF driver helper&lt;BR /&gt;mmc0: no vqmmc regulator found&lt;BR /&gt;mmc0: no vmmc regulator found&lt;BR /&gt;mmc0: SDHCI controller on 2190000.usdhc [2190000.usdhc] using ADMA&lt;BR /&gt;mmc2: no vqmmc regulator found&lt;BR /&gt;mmc2: no vmmc regulator found&lt;BR /&gt;mmc2: SDHCI controller on 2198000.usdhc [2198000.usdhc] using ADMA&lt;BR /&gt;galcore: clk_get vg clock failed, disable vg!&lt;BR /&gt;Galcore version 5.0.11.25762&lt;BR /&gt;mmc2: new ultra high speed DDR50 SDHC card at address 0007&lt;BR /&gt;mmcblk2: mmc2:0007 SS08G 7.21 GiB &lt;BR /&gt;&amp;nbsp;mmcblk2: p1 p2&lt;BR /&gt;mxc_vdoa 21e4000.vdoa: i.MX Video Data Order Adapter(VDOA) driver probed&lt;BR /&gt;mxc_vpu 2040000.vpu: VPU initialized&lt;BR /&gt;caam 2100000.caam: Instantiated RNG4 SH0&lt;BR /&gt;caam 2100000.caam: Instantiated RNG4 SH1&lt;BR /&gt;caam 2100000.caam: device ID = 0x0a160100 (Era 4)&lt;BR /&gt;caam 2100000.caam: job rings = 2, qi = 0&lt;BR /&gt;caam algorithms registered in /proc/crypto&lt;BR /&gt;caam_jr 2101000.jr0: registering rng-caam&lt;BR /&gt;platform caam_sm: blkkey_ex: 4 keystore units available&lt;BR /&gt;platform caam_sm: 64-bit clear key:&lt;BR /&gt;platform caam_sm: [0000] 00 01 02 03 04 0f 06 07&lt;BR /&gt;platform caam_sm: 64-bit black key:&lt;BR /&gt;platform caam_sm: [0000] 3e 6c 10 93 0f cb 9a 1c&lt;BR /&gt;platform caam_sm: [0008] f7 82 ca 3a 42 52 1e 19&lt;BR /&gt;platform caam_sm: 128-bit clear key:&lt;BR /&gt;platform caam_sm: [0000] 00 01 02 03 04 0f 06 07&lt;BR /&gt;platform caam_sm: [0008] 08 09 0a 0b 0c 0d 0e 0f&lt;BR /&gt;platform caam_sm: 128-bit black key:&lt;BR /&gt;platform caam_sm: [0000] 0b 12 03 60 38 fe eb 6b&lt;BR /&gt;platform caam_sm: [0008] 51 ec 7b ff 91 d0 8e d7&lt;BR /&gt;platform caam_sm: 192-bit clear key:&lt;BR /&gt;platform caam_sm: [0000] 00 01 02 03 04 0f 06 07&lt;BR /&gt;platform caam_sm: [0008] 08 09 0a 0b 0c 0d 0e 0f&lt;BR /&gt;platform caam_sm: [0016] 10 11 12 13 14 15 16 17&lt;BR /&gt;platform caam_sm: 192-bit black key:&lt;BR /&gt;platform caam_sm: [0000] 50 0d f6 ae 32 c7 3b a0&lt;BR /&gt;platform caam_sm: [0008] 6c db fb 85 c5 c9 7d b1&lt;BR /&gt;platform caam_sm: [0016] a8 b5 42 7a 45 67 74 c2&lt;BR /&gt;platform caam_sm: [0024] 37 c7 f3 4a 2b b3 b5 24&lt;BR /&gt;platform caam_sm: 256-bit clear key:&lt;BR /&gt;platform caam_sm: [0000] 00 01 02 03 04 0f 06 07&lt;BR /&gt;platform caam_sm: [0008] 08 09 0a 0b 0c 0d 0e 0f&lt;BR /&gt;platform caam_sm: [0016] 10 11 12 13 14 15 16 17&lt;BR /&gt;platform caam_sm: [0024] 18 19 1a 1b 1c 1d 1e 1f&lt;BR /&gt;platform caam_sm: 256-bit black key:&lt;BR /&gt;platform caam_sm: [0000] 2e b2 86 8c 6c 5c 6f 43&lt;BR /&gt;platform caam_sm: [0008] 34 18 3f 7c 84 1a e8 72&lt;BR /&gt;platform caam_sm: [0016] 8f fa 01 95 4b ab 46 16&lt;BR /&gt;platform caam_sm: [0024] c1 20 e1 dc 98 fc 6a 4b&lt;BR /&gt;platform caam_sm: 64-bit unwritten blob:&lt;BR /&gt;platform caam_sm: [0000] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0008] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0016] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0024] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0032] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0040] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0048] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0056] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0064] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0072] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0080] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0088] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: 128-bit unwritten blob:&lt;BR /&gt;platform caam_sm: [0000] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0008] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0016] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0024] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0032] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0040] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0048] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0056] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0064] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0072] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0080] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0088] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: 196-bit unwritten blob:&lt;BR /&gt;platform caam_sm: [0000] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0008] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0016] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0024] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0032] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0040] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0048] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0056] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0064] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0072] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0080] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0088] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: 256-bit unwritten blob:&lt;BR /&gt;platform caam_sm: [0000] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0008] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0016] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0024] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0032] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0040] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0048] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0056] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0064] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0072] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0080] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0088] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: 64-bit black key in blob:&lt;BR /&gt;platform caam_sm: [0000] 1c be 68 36 79 8f 44 cf&lt;BR /&gt;platform caam_sm: [0008] b5 49 58 c9 23 65 a0 29&lt;BR /&gt;platform caam_sm: [0016] af e2 0a bb 6d a2 af 9b&lt;BR /&gt;platform caam_sm: [0024] 2e 2a 88 22 6a 7e 11 36&lt;BR /&gt;platform caam_sm: [0032] 99 73 cd de c5 5e c8 e4&lt;BR /&gt;platform caam_sm: [0040] 0f 49 65 10 52 f3 86 d5&lt;BR /&gt;platform caam_sm: [0048] 70 7d fe 86 98 37 e6 13&lt;BR /&gt;platform caam_sm: [0056] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0064] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0072] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0080] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0088] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: 128-bit black key in blob:&lt;BR /&gt;platform caam_sm: [0000] ab 62 68 c4 15 95 9e 35&lt;BR /&gt;platform caam_sm: [0008] 78 83 bf 9d 97 ac 66 f4&lt;BR /&gt;platform caam_sm: [0016] 6c 13 c2 d7 cd 6a a0 a4&lt;BR /&gt;platform caam_sm: [0024] 17 9e 6b fa 2a a0 3d 92&lt;BR /&gt;platform caam_sm: [0032] 07 70 43 0c 3c ee 86 80&lt;BR /&gt;platform caam_sm: [0040] 36 e5 09 ef 51 29 1e 4b&lt;BR /&gt;platform caam_sm: [0048] 8e f9 20 4a e4 2e bd 2d&lt;BR /&gt;platform caam_sm: [0056] 0d 0c ce c2 29 58 4d e9&lt;BR /&gt;platform caam_sm: [0064] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0072] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0080] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0088] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: 192-bit black key in blob:&lt;BR /&gt;platform caam_sm: [0000] 1f 20 32 de 1d b5 9e 90&lt;BR /&gt;platform caam_sm: [0008] 85 bb e8 d7 ff b0 b5 74&lt;BR /&gt;platform caam_sm: [0016] b5 85 f0 b3 43 65 a1 b6&lt;BR /&gt;platform caam_sm: [0024] 90 43 67 96 79 af d4 c9&lt;BR /&gt;platform caam_sm: [0032] 57 88 f1 33 13 60 25 76&lt;BR /&gt;platform caam_sm: [0040] ab 3b 25 87 c3 af 1c c1&lt;BR /&gt;platform caam_sm: [0048] 67 00 fd 5d c9 86 1f 94&lt;BR /&gt;platform caam_sm: [0056] c9 01 d9 c3 a4 65 8a 7f&lt;BR /&gt;platform caam_sm: [0064] 14 25 64 33 33 1c 6d 59&lt;BR /&gt;platform caam_sm: [0072] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0080] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0088] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: 256-bit black key in blob:&lt;BR /&gt;platform caam_sm: [0000] 8e ab 05 f6 21 6c 90 b8&lt;BR /&gt;platform caam_sm: [0008] 1c 99 ce 31 87 d2 2a fc&lt;BR /&gt;platform caam_sm: [0016] fd 99 79 64 78 be 53 2a&lt;BR /&gt;platform caam_sm: [0024] 03 49 bc ed 71 10 31 09&lt;BR /&gt;platform caam_sm: [0032] a8 4e ee 8c dd c8 06 8b&lt;BR /&gt;platform caam_sm: [0040] a8 ee eb 01 99 ac e9 14&lt;BR /&gt;platform caam_sm: [0048] 1a 4d de 82 57 84 e1 61&lt;BR /&gt;platform caam_sm: [0056] 85 7a 55 9f 68 8c 06 c2&lt;BR /&gt;platform caam_sm: [0064] 53 86 b0 b0 c0 f5 17 28&lt;BR /&gt;platform caam_sm: [0072] d4 55 db 1e 8c 79 a1 9f&lt;BR /&gt;platform caam_sm: [0080] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: [0088] 00 00 00 00 00 00 00 00&lt;BR /&gt;platform caam_sm: restored 64-bit black key:&lt;BR /&gt;platform caam_sm: [0000] 74 aa e3 98 f9 99 48 71&lt;BR /&gt;platform caam_sm: [0008] fe 58 60 e2 8f 95 3d 29&lt;BR /&gt;platform caam_sm: restored 128-bit black key:&lt;BR /&gt;platform caam_sm: [0000] 0b 12 03 60 38 fe eb 6b&lt;BR /&gt;platform caam_sm: [0008] 51 ec 7b ff 91 d0 8e d7&lt;BR /&gt;platform caam_sm: restored 192-bit black key:&lt;BR /&gt;platform caam_sm: [0000] 50 0d f6 ae 32 c7 3b a0&lt;BR /&gt;platform caam_sm: [0008] 6c db fb 85 c5 c9 7d b1&lt;BR /&gt;platform caam_sm: [0016] 18 ab 4a b8 38 b0 d9 80&lt;BR /&gt;platform caam_sm: [0024] 48 fb 2f 2f 53 72 79 50&lt;BR /&gt;platform caam_sm: restored 256-bit black key:&lt;BR /&gt;platform caam_sm: [0000] 2e b2 86 8c 6c 5c 6f 43&lt;BR /&gt;platform caam_sm: [0008] 34 18 3f 7c 84 1a e8 72&lt;BR /&gt;platform caam_sm: [0016] 8f fa 01 95 4b ab 46 16&lt;BR /&gt;platform caam_sm: [0024] c1 20 e1 dc 98 fc 6a 4b&lt;BR /&gt;snvs-secvio 20cc000.caam-snvs: violation handlers armed - non-secure state&lt;BR /&gt;usbcore: registered new interface driver usbhid&lt;BR /&gt;usbhid: USB HID core driver&lt;BR /&gt;cs42xx8 1-0048: failed to get device ID, ret = -5&lt;BR /&gt;cs42xx8: probe of 1-0048 failed with error -5&lt;BR /&gt;fsl-asrc 2034000.asrc: driver registered&lt;BR /&gt;fsl-hdmi-dai hdmi_audio.3: failed to probe. Load HDMI-video first.&lt;BR /&gt;fsl-hdmi-dai: probe of hdmi_audio.3 failed with error -12&lt;BR /&gt;imx-cs42888 sound-cs42888.25: failed to find codec platform device&lt;BR /&gt;imx-cs42888: probe of sound-cs42888.25 failed with error -22&lt;BR /&gt;imx-spdif sound-spdif.20: snd-soc-dummy-dai &amp;lt;-&amp;gt; 2004000.spdif mapping ok&lt;BR /&gt;imx-audio-hdmi sound-hdmi.21: initialize HDMI-audio failed. load HDMI-video first!&lt;BR /&gt;imx-tuner-si476x sound-fm.30: failed to find FM platform device&lt;BR /&gt;imx-tuner-si476x: probe of sound-fm.30 failed with error -22&lt;BR /&gt;NET: Registered protocol family 26&lt;BR /&gt;TCP: cubic registered&lt;BR /&gt;NET: Registered protocol family 10&lt;BR /&gt;sit: IPv6 over IPv4 tunneling driver&lt;BR /&gt;NET: Registered protocol family 17&lt;BR /&gt;can: controller area network core (rev 20120528 abi 9)&lt;BR /&gt;NET: Registered protocol family 29&lt;BR /&gt;can: raw protocol (rev 20120528)&lt;BR /&gt;can: broadcast manager protocol (rev 20120528 t)&lt;BR /&gt;can: netlink gateway (rev 20130117) max_hops=1&lt;BR /&gt;Bluetooth: RFCOMM TTY layer initialized&lt;BR /&gt;Bluetooth: RFCOMM socket layer initialized&lt;BR /&gt;Bluetooth: RFCOMM ver 1.11&lt;BR /&gt;Bluetooth: BNEP (Ethernet Emulation) ver 1.3&lt;BR /&gt;Bluetooth: BNEP filters: protocol multicast&lt;BR /&gt;Bluetooth: BNEP socket layer initialized&lt;BR /&gt;Bluetooth: HIDP (Human Interface Emulation) ver 1.2&lt;BR /&gt;Bluetooth: HIDP socket layer initialized&lt;BR /&gt;8021q: 802.1Q VLAN Support v1.8&lt;BR /&gt;Key type dns_resolver registered&lt;BR /&gt;failed to disable 1.2 GHz OPP&lt;BR /&gt;VGEN2: disabling&lt;BR /&gt;SWBST: disabling&lt;BR /&gt;SW4: disabling&lt;BR /&gt;regulator-dummy: disabling&lt;BR /&gt;imx mcc test is registered.&lt;BR /&gt;usb_h1_vbus: 5000 mV &lt;BR /&gt;usb_otg_vbus: 5000 mV &lt;BR /&gt;ci_hdrc ci_hdrc.1: doesn't support gadget&lt;BR /&gt;ci_hdrc ci_hdrc.1: EHCI Host Controller&lt;BR /&gt;ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1&lt;BR /&gt;ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00&lt;BR /&gt;hub 1-0:1.0: USB hub found&lt;BR /&gt;hub 1-0:1.0: 1 port detected&lt;BR /&gt;input: gpio-keys.18 as /devices/soc0/gpio-keys.18/input/input1&lt;BR /&gt;snvs_rtc 20cc034.snvs-rtc-lp: setting system clock to 1970-01-01 00:00:02 UTC (2)&lt;BR /&gt;ALSA device list:&lt;BR /&gt;&amp;nbsp; #0: imx-spdif&lt;BR /&gt;kjournald starting.&amp;nbsp; Commit interval 5 seconds&lt;BR /&gt;EXT3-fs (mmcblk2p2): using internal journal&lt;BR /&gt;EXT3-fs (mmcblk2p2): recovery complete&lt;BR /&gt;EXT3-fs (mmcblk2p2): mounted filesystem with ordered data mode&lt;BR /&gt;VFS: Mounted root (ext3 filesystem) on device 179:2.&lt;BR /&gt;devtmpfs: mounted&lt;BR /&gt;Freeing unused kernel memory: 328K (80d15000 - 80d67000)&lt;BR /&gt;INIT: version 2.88 booting&lt;BR /&gt;Starting udev&lt;BR /&gt;udevd[177]: starting version 182&lt;BR /&gt;ERROR: v4l2 capture: slave not found!&lt;BR /&gt;FAT-fs (mmcblk2p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.&lt;BR /&gt;bootlogd: cannot allocate pseudo tty: No such file or directory&lt;BR /&gt;random: dd urandom read with 81 bits of entropy available&lt;BR /&gt;ALSA: Restoring mixer settings...&lt;BR /&gt;No state is present for card imxspdif&lt;BR /&gt;Found hardware: "imx-spdif" "" "" "" ""&lt;BR /&gt;Hardware is initialized using a generic method&lt;BR /&gt;No state is present for card imxspdif&lt;BR /&gt;Fri Feb&amp;nbsp; 3 11:37:18 UTC 2017&lt;BR /&gt;INIT: Entering runlevel: 5&lt;BR /&gt;Configuring network interfaces... fec 2188000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=2188000.ethernet:01, irq=-1)&lt;BR /&gt;IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready&lt;BR /&gt;done.&lt;BR /&gt;Starting Xserver&lt;BR /&gt;Starting system message bus: dbus.&lt;BR /&gt;Starting Connection Manager&lt;BR /&gt;Starting Dropbear SSH server: dropbear.&lt;BR /&gt;Starting rpcbind daemon...done.&lt;BR /&gt;mipi_dsi 21e0000.mipi:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; write_reg:0x04, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; write_reg:0x54, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; write_reg:0x08, val:0x00000107.&lt;BR /&gt;mipi_dsi 21e0000.mipi:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; write_reg:0x0c, val:0x000000e0.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;^Cmipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;^Cmipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;^Cmipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;^Cmipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;^Cmipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80!&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x44, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x48, val:0x00000080.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x50, val:0x00000000.&lt;BR /&gt;mipi_dsi 21e0000.mipi: read_reg:0x4c, val:0x00000000.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;CPU:&amp;nbsp;&amp;nbsp; Temperature 27 C, calibration data: 0x5b34fa7d&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Original Attachment has been moved to: &lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-336729"&gt;mxcfb_hx8369_wvga.c.zip&lt;/A&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Apr 2017 14:34:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Mipi-OLED-interface-errors-after-interfacing/m-p/662437#M101700</guid>
      <dc:creator>kunalkulshresth</dc:creator>
      <dc:date>2017-04-10T14:34:08Z</dc:date>
    </item>
    <item>
      <title>Re: Mipi OLED interface errors after interfacing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Mipi-OLED-interface-errors-after-interfacing/m-p/662438#M101701</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Kunal&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please check attached Linux Manual Chapter 7 MIPI DSI Driver.&lt;/P&gt;&lt;P&gt;For 400x400 resolution fb_videomode truly_lcd_modedb[], mxcfb_hx8369_wvga.c&lt;/P&gt;&lt;P&gt;should be customized with new panel timings. Also&amp;nbsp;manufacturer init code&lt;/P&gt;&lt;P&gt;should be placed in mipid_hx8369_lcd_setup().&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Apr 2017 23:35:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Mipi-OLED-interface-errors-after-interfacing/m-p/662438#M101701</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-04-10T23:35:39Z</dc:date>
    </item>
    <item>
      <title>Re: Mipi OLED interface errors after interfacing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Mipi-OLED-interface-errors-after-interfacing/m-p/662439#M101702</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks. I have tried to configure these functions as per datasheet of oled. Any idea how to test the fb linked with Mipi interface working? I mean I want to quickly try with a test that tries to show some dummy image on the OLED. Please let me know if there are some relevant tests to verify mipi interface. I tested using DSO, the clock and data line show some movement but oled display still black. Need help.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks and regards,&lt;/P&gt;&lt;P&gt;Kunal&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Apr 2017 08:49:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Mipi-OLED-interface-errors-after-interfacing/m-p/662439#M101702</guid>
      <dc:creator>kunalkulshresth</dc:creator>
      <dc:date>2017-04-17T08:49:08Z</dc:date>
    </item>
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