topic PCIe memory alignment and size in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/PCIe-memory-alignment-and-size/m-p/661862#M101616 <HTML><HEAD></HEAD><BODY><P>we have 4&nbsp;EP devices each have 8MB access requirement.</P><P>but i can read from manual "PCIe max memory alignment is 16MB for i.MX 6 quad."</P><P></P><P>Can i.MX 6 access 4&nbsp;EP devices each have 8MB ?</P><P></P><P>In iATU, it can has 4 regions. then</P><P>first iATU set : 8MB &nbsp;for first EP</P><P>second iATU set : 8MB for second EP</P><P>third iATU set : 8MB for third EP</P><P>fourth iATU set : 8MB for fourth EP</P><P>is it possible ?</P></BODY></HTML> Mon, 24 Oct 2016 02:16:27 GMT jimmykwon 2016-10-24T02:16:27Z PCIe memory alignment and size https://community.nxp.com/t5/i-MX-Processors/PCIe-memory-alignment-and-size/m-p/661862#M101616 <HTML><HEAD></HEAD><BODY><P>we have 4&nbsp;EP devices each have 8MB access requirement.</P><P>but i can read from manual "PCIe max memory alignment is 16MB for i.MX 6 quad."</P><P></P><P>Can i.MX 6 access 4&nbsp;EP devices each have 8MB ?</P><P></P><P>In iATU, it can has 4 regions. then</P><P>first iATU set : 8MB &nbsp;for first EP</P><P>second iATU set : 8MB for second EP</P><P>third iATU set : 8MB for third EP</P><P>fourth iATU set : 8MB for fourth EP</P><P>is it possible ?</P></BODY></HTML> Mon, 24 Oct 2016 02:16:27 GMT https://community.nxp.com/t5/i-MX-Processors/PCIe-memory-alignment-and-size/m-p/661862#M101616 jimmykwon 2016-10-24T02:16:27Z Re: PCIe memory alignment and size https://community.nxp.com/t5/i-MX-Processors/PCIe-memory-alignment-and-size/m-p/661863#M101617 <HTML><HEAD></HEAD><BODY><P>Q. Can i.MX 6 access 4 EP devices each have 8MB ?</P><P></P><P>A. Unfortunately, no. The total amount of memory for all endpoints is limited to 16MB.</P><P><BR />Have a great day,<BR />Artur</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Thu, 27 Oct 2016 12:07:52 GMT https://community.nxp.com/t5/i-MX-Processors/PCIe-memory-alignment-and-size/m-p/661863#M101617 art 2016-10-27T12:07:52Z