topic Re: ENETx_ECR settings in i.MX6SoloX in i.MX Processors

ENETx_ECR settings in i.MX6SoloX

ko-hey — Fri, 30 Sep 2016 04:32:00 GMT

Hi all

I'm using i.MX6SoloX and have a question about RGMII interface.

I want to set RXC_DLY and TXC_DLY field of ENETx_ECR register and try following flow.
But both fields aren't able to set "1".

The BSP is L4.1.15 and the tool which I used is memtool.

Here is my tried flow and the result.
-----------------------------------
root@imx6sx_all:/unit_tests# ./memtool -32 02188024=70030012
Writing 32-bit value 0x70030012 to address 0x02188024
root@imx6sx_all:/unit_tests# ./memtool -32 02188024 10
E
Reading 0x10 count starting at address 0x02188024

0x02188024: 70000012 00000000 00000000 00000000
0x02188034: 00000000 00000000 00000000 611215E1
0x02188044: 0000001A 00000000 00000000 00000000
0x02188054: 00000000 00000000 00000000 00000000
-----------------------------------

Also I read a P1098 of reference manual.

It seems that RXC_DLY and TXC_DLY can set "1".

Can RXC_DLY and TXC_DLY set to "1" ?
If yes, please tell me how to do.

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

Yuri — Fri, 30 Sep 2016 09:26:24 GMT

Hello,

What is exact part number number of the i.MX6 SX ?

In the previous RM release regrading ENETx_ECR :
bits 31–12 : This field is reserved. This field must be set to 7_0000h.

Have a great day,
Yuri

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Re: ENETx_ECR settings in i.MX6SoloX

ko-hey — Fri, 30 Sep 2016 09:50:58 GMT

Hi Yuri

I'm not sure their part number.

However, I tried same way with MCIMX6X-SDB.

Do you mean that it depends on the device revision ?

According to the latest datasheet, user can set 16 and 17 field.

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

ko-hey — Mon, 03 Oct 2016 04:37:43 GMT

Hi Yuri

Here is additional info.

They use MCIMX6X4EVM10AB.

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

Yuri — Mon, 03 Oct 2016 05:41:53 GMT

Hello,

I expect it may work only for the rev.1.3 : mask 3N19K

Regards,

Yuri.

Re: ENETx_ECR settings in i.MX6SoloX

ko-hey — Mon, 03 Oct 2016 07:08:09 GMT

Is that a errata ?

I couldn't find about it on the latest errata document.

http://www.nxp.com/files/32bit/doc/errata/IMX6SXCE.pdf

Also I can't find on "Silicon Revision 1.2 to 1.3 Comparison"

http://www.nxp.com/files/microcontrollers/doc/eng_bulletin/EB832.pdf

> I expect it may work only for the rev.1.3 : mask 3N19K.

Could you check it to expert engineer ?

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

Yuri — Mon, 03 Oct 2016 08:58:36 GMT

Internal :
https://community.nxp.com/thread/435880

Re: ENETx_ECR settings in i.MX6SoloX

ko-hey — Tue, 04 Oct 2016 01:10:42 GMT

Hi Yuri

I can't open it.

If I open the SR, can you share me again ?

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

Yuri — Tue, 04 Oct 2016 04:42:14 GMT

It is internal link - just for me.

~Yuri.

Re: ENETx_ECR settings in i.MX6SoloX

ko-hey — Tue, 04 Oct 2016 05:09:21 GMT

Hi Yuri

Okay, so the conclusion is as follow.

Rev 1.2 ?Production (Maskset 2N19K) ⇒ ENETx_ECR can't overwrite.

Rev 1.3 ?Production (Maskset 3N19K) ⇒ ENETx_ECR can overwrite.

Is it correct ?

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

Yuri — Thu, 13 Oct 2016 07:22:48 GMT

Hello,

From the team :

" i.MX6SX doesn't have that feature".

Regards,

Yuri.

Re: ENETx_ECR settings in i.MX6SoloX

ko-hey — Thu, 13 Oct 2016 08:22:09 GMT

I can't understand your reply.

You said that if they use Rev 1.3(Maskset 3N19K), ENETx_ECR can't overwrite.

Is it correct ?

I want to clear whether the ENETx_ECR can change their value or not.

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

Yuri — Fri, 14 Oct 2016 07:35:28 GMT

Hello,

RXC_DLY and TXC_DLY fields are not functional in any i.MX6SX releases.

Regards,

Yuri.

Re: ENETx_ECR settings in i.MX6SoloX

ko-hey — Fri, 14 Oct 2016 07:44:40 GMT

Hi Yuri

Thank you for check to Design Engineer.

Do you have any plan to add to the errata ?

Or will you revise the datasheet ?

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

Yuri — Mon, 17 Oct 2016 04:47:29 GMT

Hello,

request for the Reference Manual correction was added.

Regards,

Yuri.

Re: ENETx_ECR settings in i.MX6SoloX

ko-hey — Mon, 17 Oct 2016 07:24:33 GMT

Hi Yuri

Thank you for reply.

I understood.

Ko-hey

Re: ENETx_ECR settings in i.MX6SoloX

MichaelV — Fri, 01 Mar 2024 20:53:09 GMT

The same seems to be true for iMX6Q?

------------------ System Information ------------------ Processor = iMX6 Quad (4 cores) Speed grade = 996 MHz (core @ 996 MHz) Temperature grade = Automotive -40 to 125C Chip silicon revision = 1.3 \> memtool 0x2188024=0xF0030112 Writing 1 DWORD(s) to physical address 0x2188024... \> memtool 0x2188024 Reading 1 DWORD(s) from physical address 0x2188024... 0x02188024: F0000112

As you can see, ENET_ECR[17:16] also don't stick in the iMX6 Quad. I guess these bits are non-functional in all iMX variants?