imx53 LPDDR2 configuration

danix — Sat, 10 Dec 2011 05:47:34 GMT

Hi all,

I nedd help on interfacing LPDDR2 with imx535 (529 BGA). I'm using the micron MT42L128M32D2 mounted on PCB.

I want to get the proper initialization code and also advise on the interconnection and layout. I don't seem to find official documents on this.

Any help would be appreciated

Re: imx53 LPDDR2 configuration

pierreschirrer — Fri, 02 Oct 2015 06:40:44 GMT

Hello Danix,

I have designed a board with an i.MX53 and LPDDR2 from Micron : MT42L256M32D2. It should be straightforward to interface the smaller package you need. I have also derived (with some trial and error) the initialization of the DDR controller. I can share the connection diagram with you (preferrably with a direct link) and the initialization can be found below. Please forward your email address for the schematic.

Regards.

Init file for LPDDR2:

// Add a forced HW ZQ

wait = on

//*================================================================================================

// Disable WDOG

//*================================================================================================

//setmem /16 0x53f98000 = 0x30

//*================================================================================================

// Enable all clocks (they are disabled by ROM code)

//*================================================================================================

//setmem /32 0x53fd4018 = 0x00016554 // unmask line for DDR @ 200MHz

setmem /32 0x53fd4068 = 0xffffffff

setmem /32 0x53fd406c = 0xffffffff

setmem /32 0x53fd4070 = 0xffffffff

setmem /32 0x53fd4074 = 0xffffffff

setmem /32 0x53fd4078 = 0xffffffff

setmem /32 0x53fd407c = 0xffffffff

setmem /32 0x53fd4080 = 0xffffffff

setmem /32 0x53fd4084 = 0xffffffff

//*================================================================================================

// Initialization script for 32 bit DDR2 (CS0+CS1)

//*================================================================================================

// DDR2 IOMUX configuration

setmem /32 0x53fa8554 = 0x00280000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

setmem /32 0x53fa8560 = 0x00280000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

setmem /32 0x53fa8594 = 0x00280000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

setmem /32 0x53fa8584 = 0x00280000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

setmem /32 0x53fa8558 = 0x002800c0 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 enable pull down

setmem /32 0x53fa8568 = 0x002800c0 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 enable pull down

setmem /32 0x53fa8590 = 0x002800c0 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 enable pull down

setmem /32 0x53fa857c = 0x002800c0 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 enable pull down

setmem /32 0x53fa872c = 0x00280000 //IOMUXC_SW_PAD_CTL_GRP_B3DS

setmem /32 0x53fa8728 = 0x00280000 //IOMUXC_SW_PAD_CTL_GRP_B2DS

setmem /32 0x53fa871c = 0x00280000 //IOMUXC_SW_PAD_CTL_GRP_B1DS

setmem /32 0x53fa8718 = 0x00280000 //IOMUXC_SW_PAD_CTL_GRP_B0DS

setmem /32 0x53fa8570 = 0x00280000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

setmem /32 0x53fa8578 = 0x00280000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

//setmem /32 0x53fa8564 = 0x00300040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

//setmem /32 0x53fa8580 = 0x00300040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

//setmem /32 0x53fa8574 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

//setmem /32 0x53fa8588 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

setmem /32 0x53fa86f0 = 0x00280000 //IOMUXC_SW_PAD_CTL_GRP_ADDDS

setmem /32 0x53fa86fc = 0x00000000 //IOMUXC_SW_PAD_CTL_GRP_DDRPKE

setmem /32 0x53fa8720 = 0x00280000 //IOMUXC_SW_PAD_CTL_GRP_CTLDS

setmem /32 0x53fa86f4 = 0x00000200 //IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL

setmem /32 0x53fa8714 = 0x00000000 //IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode

setmem /32 0x53fa8724 = 0x06000000 //IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=11

//Set this mode, as LPDDR2 is used @ 1.2V and the ZQ resistor is 160 Ohms (! DDR_SEL=10 as one would expect does not work !)

//setmem /32 0x63fd9098 = 0x00000f00 //add 3 logic unit of delay to sdclk to improve EVK DDR max frequency

//read delays:

//setmem /32 0x63fd905c = 0x33333333 //all byte 0 data delayed by 3

//setmem /32 0x63fd9060 = 0x33333333 //all byte 1 data delayed by 3

//setmem /32 0x63fd9064 = 0x33333333 //all byte 2 data delayed by 3

//setmem /32 0x63fd9068 = 0x33333333 //all byte 3 data delayed by 3

//write delays:

//setmem /32 0x63fd906c = 0xf3333333 //all byte 0 data & dm delayed by 3

//setmem /32 0x63fd9070 = 0xf3333333 //all byte 1 data & dm delayed by 3

//setmem /32 0x63fd9074 = 0xf3333333 //all byte 2 data & dm delayed by 3

//setmem /32 0x63fd9078 = 0xf3333333 //all byte 3 data & dm delayed by 3

// Initialize LPDDR2 memory - Micron MT42L256M32D2

//setmem /32 0x63fd909c = 0x3f8f018f // ZQLP2CTL

//setmem /32 0x63fd909c = 0x63c801ff

// ZQcs=0x63 100 cyc, ok to support 96ns

// ZQcl=0xc8 200 cyc, to support 360ns with 2ns cycle

// ZQinit =0x1ff , to support 1uS with 2ns cyc

setmem /32 0x63fd909c = 0x638f018f

// ZQcs=0x63 Default to 100 cyc, ok to support 96ns (250ns)

// ZQcl=0x8f 144 cyc, default JEDEC value for 360ns with 2.5 ns cycle

// ZQinit =0x18f 400 cyc, default JEDEC value for 1uS with 2.5ns cyc

setmem /32 0x63fd9088 = 0x3633342e //set the already measured rd delay vals

setmem /32 0x63fd9090 = 0x504f5049 //set the already measured wr delay vals

//setmem /32 0x63fd9088 = 0x3630332a //set the already measured rd delay vals

//setmem /32 0x63fd9090 = 0x5250524b //set the already measured wr delay vals

//setmem /32 0x63fd9088 = 0x40404040

//setmem /32 0x63fd9090 = 0x40404040

setmem /32 0x63fd90f8 = 0x00000800 //force the above two registers measured content into SDCTL.

setmem /32 0x63fd907c = 0x20000000 //dqs_gating disable

//setmem /32 0x63fd9018 = 0x000016c8 // Enable bank interleaving, RALAT = 0x3, DDR_TYPE = LPDDR2

//setmem /32 0x63fd9018 = 0x00001748 // Enable bank interleaving, RALAT = 0x5, DDR_TYPE = LPDDR2

//setmem /32 0x63fd9018 = 0x00000ec8 // Disable bank interleaving, -S4 LPDDR2, RALAT = 0x3, 8 banks devices, DDR_TYPE = LPDDR2

//setmem /32 0x63fd9000 = 0xc3010000 // Enable CSD0 and CSD1, row width = 14, column width = 9, Burst length 4, data width = 32bit

setmem /32 0x63fd9018 = 0x00001f48 // Enable bank interleaving, RALAT = 0x5, DDR_TYPE = LPDDR2-S4 with 8 banks

setmem /32 0x63fd9000 = 0xc3110000 // Enable CSD0 and CSD1, row width = 14, column width = 10, Burst length 4, data width = 32bit

//setmem /32 0x63fd900C = 0x33374733 // tRFC = 52 ck, tXS = 56 ck, tXP = 3 ck, tFAW = 19 ck, CAS latency = 6 ck

setmem /32 0x63fd900c = 0x33374733 // tRFC = 52 ck, tXS = 56 ck, tXP = 3 ck, tFAW = 20 ck, CAS latency = 6 ck

//setmem /32 0x63fd9010 = 0x00118a82 // tRCD=tRP=tRC=0, tRAS = 18 ck, tRPA = 1, tWR = 6 ck, tMRD = 5 ck, tCWL = 3 ck

setmem /32 0x63fd9010 = 0x00118a62 // tRCD=tRP=tRC=0, tRAS = 17 ck, tRPA = 1, tWR = 6 ck, tMRD = 3 ck, tCWL = 3 ck

setmem /32 0x63fd9014 = 0x00c70093 // tDLLK(tXSRD) = 200 cycles, tRTP = 3 ck, tWTR = 3ck, tRRD = 4ck

//setmem /32 0x63fd9038 = 0x00190778 // tRC=25, tRCD = 8ck, tRPPB = 8ck, tRPAB = 9ck

setmem /32 0x63fd9038 = 0x00190778 // tRC=26 ck, tRCD = 8ck, tRPPB = 8ck, tRPAB = 9ck

//setmem /32 0x63fd902c = 0x079726d2

setmem /32 0x63fd902c = 0x0f9f26d2 // tDAI = 4000 cyc, reset default

setmem /32 0x63fd9030 = 0x009f000e // Not relevant LPDDR2

setmem /32 0x63fd9008 = 0x12272000 // Not relevant LPDDR2

setmem /32 0x63fd9004 = 0x00030024 // tCKE = 3 ck, tCKSRX = 4 cyc, tCKSRE = 4 cyc

setmem /32 0x63fd901c = 0x003f8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 : RESET

setmem /32 0x63fd901c = 0x003f8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 : RESET

setmem /32 0x63fd901c = 0xff0a8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff : Calibration after init

setmem /32 0x63fd901c = 0xff0a8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff : Calibration after init

setmem /32 0x63fd901c = 0x82018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=82 : nWR=6ck, Wrap, Seq burst, BL=4

setmem /32 0x63fd901c = 0x82018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=82 : nWR=6ck, Wrap, Seq burst, BL=4

setmem /32 0x63fd901c = 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=4 : RL6, WL3 => 400 MHz

setmem /32 0x63fd901c = 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=4 : RL6, WL3 => 400 MHz

setmem /32 0x63fd901c = 0x01038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=1 : Drive strength 34.3 ohms

setmem /32 0x63fd901c = 0x01038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=1 : Drive strength 34.3 ohms

//setmem /32 0x63fd9020 = 0x00005800

setmem /32 0x63fd9020 = 0x00007800 // 8 refreshs , 32kHz rate

//setmem /32 0x63fd9020 = 0x00001800 // 4 refreshs , 64kHz rate

//setmem /32 0x63fd9040 = 0x04b80003 // ZQ HW control

setmem /32 0x63fd9040 = 0xa5390003 // ZQ HW control: Parallel, 128 cyc, 256 cyc, 512 cyc

setmem /32 0x63fd901c = 0x00000000

topic imx53 LPDDR2 configuration in i.MX Processors

imx53 LPDDR2 configuration

Re: imx53 LPDDR2 configuration