topic Re: For a custom parallel display, best driver to modify? in i.MX Processors

For a custom parallel display, best driver to modify?

robertspriggs — Thu, 08 Dec 2016 14:14:39 GMT

Hi,

I'm trying to add a custom display to the DISP lines of an i.MX6DL (actually the signal goes to an FPGA.) I've been finding it difficult to find documentation and attempted to use the LDB driver as there seems to be the most info available on that. However, I don't think this is right for our application. Our FPGA expects to get parallel data (16 bits) in YUV format, one pixel per clock, NOT SPWG or JEIDA formatted data... So my question here is, which MXC driver would be best (easiest?) to modify for our application? Ideally we want to be able to do 1080p60, but at least be able to do 720p60 and 1080i60.

Re: For a custom parallel display, best driver to modify?

igorpadykov — Thu, 08 Dec 2016 23:44:21 GMT

Hi Robert

seems best starting point would be mxc_lcdif.c, please check

Table 6-1. IPU Driver Files attached Linux Manual.

Best regards
igor
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Re: For a custom parallel display, best driver to modify?

robertspriggs — Wed, 14 Dec 2016 17:01:34 GMT

Thanks Igor,

I've got the LCD driver going, but I seem to be having an issue similar to the LDB clock issue where u-boot was setting the wrong clock, and the clock could not be changed in Linux. Is this a known issue for the LCD? Are there any documents on setting the clocks for the lcdif driver?

I looked for the registers related to the IPU clock these are the values I'm reading:

(The processor is i.MX6DL so it only has 1 IPU, and only one display so I'm only concerned with D0)

CCM_CHSCCDR addr: 20C_4034h = 0x00012090

IPU di0 clock premutiplexer(8-6) = 010 = derive clock from PLL5

IPU di0 clock divider(5-3) = 010 = divide by 3

IPU di0 root clock multiplexer(2-0) = 000 = derive clock from divided pre-muxed ipu1 di0 clock

CCM_CSCDR3 addr: 20C_403Ch = 0x00014E41

Divider for IPU HSP clock(13-11) = 001 = divide by 2

Selector for IPU HSP clock multiplier(10-9) = 11 = derive clock from PLL3 PFD1

CCM_CCOSR addr: 20C_4060h = 0x000E0101

Select clock to be generated on CCM_CLKO1(3-0) = 0001 = PLL2 main clk

Select clock to be generated on CCM_CLKO1(20-16) = 01110 = osc clk

CCM_CCGR3 addr: 20C_4074h = 0x3FF00003 (not sure why there are twos bits for every field in this register)
IPU di0 clock and pre-clock enable(3-2) = 00

IPU clock(1-0) = 11

Re: For a custom parallel display, best driver to modify?

robertspriggs — Tue, 20 Dec 2016 18:48:14 GMT

So I now have two drivers putting out video, an LCDIF driver that I can't set the clock on and LDB driver that has perfect timing, but I can't set the color space (plus in YUYV16 mode I only see D0-D7 on the DISP lines.) I'm not sure which driver is best to try to get working...