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    <title>i.MX Processors中的主题 question about interrupt</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658657#M101048</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i use imx6sx-sd board and have some&amp;nbsp; question about how interrupt work&lt;/P&gt;&lt;P&gt;if i set GPIO6_2 as interrupt pin at both Cortex-A9 and Cortex-M4,when this pin is trigger,which core will handle this interrupt signal&lt;/P&gt;&lt;P&gt;i read &amp;lt;Getting_Started_with_Multicore_Programming_for_i.MX_6SoloX_V0.pdf&amp;gt; about low power function,it means that when Cortex-M4 set into low power mode , linux will close Cortex-M4 clock and&amp;nbsp; Cortex-M4 can't wake up by&amp;nbsp; interrupt direct. it only let linux register wake up interrupt souce and first wake up linux ,then linux open Cortex-M4 clock and let it run out low power mode ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 28 Sep 2016 08:21:13 GMT</pubDate>
    <dc:creator>caibai</dc:creator>
    <dc:date>2016-09-28T08:21:13Z</dc:date>
    <item>
      <title>question about interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658657#M101048</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i use imx6sx-sd board and have some&amp;nbsp; question about how interrupt work&lt;/P&gt;&lt;P&gt;if i set GPIO6_2 as interrupt pin at both Cortex-A9 and Cortex-M4,when this pin is trigger,which core will handle this interrupt signal&lt;/P&gt;&lt;P&gt;i read &amp;lt;Getting_Started_with_Multicore_Programming_for_i.MX_6SoloX_V0.pdf&amp;gt; about low power function,it means that when Cortex-M4 set into low power mode , linux will close Cortex-M4 clock and&amp;nbsp; Cortex-M4 can't wake up by&amp;nbsp; interrupt direct. it only let linux register wake up interrupt souce and first wake up linux ,then linux open Cortex-M4 clock and let it run out low power mode ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Sep 2016 08:21:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658657#M101048</guid>
      <dc:creator>caibai</dc:creator>
      <dc:date>2016-09-28T08:21:13Z</dc:date>
    </item>
    <item>
      <title>Re: question about interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658658#M101049</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi cai&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;seems you are right: please check Table 10-1. Power Modes&lt;/P&gt;&lt;P&gt;i.MX6SX Reference Manual, its shows M4 as Always Clock Gated&lt;/P&gt;&lt;P&gt;in Stop mode.&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fcache.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fref_manual%2FIMX6SXRM.pdf" rel="nofollow" target="_blank"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Sep 2016 09:41:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658658#M101049</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-09-28T09:41:51Z</dc:date>
    </item>
    <item>
      <title>Re: question about interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658659#M101050</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;thank you for reply.&lt;/P&gt;&lt;P&gt;how CPU deal&amp;nbsp; with GPIO interrupt when Cortex-A9 and Cortex-M4 both configure it as interrupt&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Sep 2016 11:21:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658659#M101050</guid>
      <dc:creator>caibai</dc:creator>
      <dc:date>2016-09-28T11:21:45Z</dc:date>
    </item>
    <item>
      <title>Re: question about interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658660#M101051</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;please check Chapter 52 Resource Domain Controller (RDC)&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Sep 2016 11:29:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/question-about-interrupt/m-p/658660#M101051</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-09-28T11:29:08Z</dc:date>
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