topic Re: I in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/I/m-p/655584#M100453 <HTML><HEAD></HEAD><BODY><P>Hi Cyrus,</P><P></P><P>this question is related to ARM Cortex processor rather that the whole NXP MCU. For instance you should identify which ARM core are you using. For details about ARM cores you may contact ARM or check their infocenter.</P><P></P><P><A href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihbiadi.html">4.2.3. Interrupt Clear-enable Register</A></P><P><A href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/Cihcajhj.html">4.2.2. Interrupt Set-enable Registers</A></P><P><BR />Regards,<BR />Carlos</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Tue, 21 Feb 2017 21:16:14 GMT Carlos_Musich 2017-02-21T21:16:14Z I https://community.nxp.com/t5/i-MX-Processors/I/m-p/655583#M100452 <HTML><HEAD></HEAD><BODY><P>Hi</P><P>I have a question about ARM architecture</P><P>why there is two registers to enable/disable interrupts? ISER and ICER</P><P>Is it not possible to set/reset the same register for enable/disabling the interrupts?</P><P>thank you</P></BODY></HTML> Tue, 21 Feb 2017 10:17:09 GMT https://community.nxp.com/t5/i-MX-Processors/I/m-p/655583#M100452 cyrusvali 2017-02-21T10:17:09Z Re: I https://community.nxp.com/t5/i-MX-Processors/I/m-p/655584#M100453 <HTML><HEAD></HEAD><BODY><P>Hi Cyrus,</P><P></P><P>this question is related to ARM Cortex processor rather that the whole NXP MCU. For instance you should identify which ARM core are you using. For details about ARM cores you may contact ARM or check their infocenter.</P><P></P><P><A href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihbiadi.html">4.2.3. Interrupt Clear-enable Register</A></P><P><A href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/Cihcajhj.html">4.2.2. Interrupt Set-enable Registers</A></P><P><BR />Regards,<BR />Carlos</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Tue, 21 Feb 2017 21:16:14 GMT https://community.nxp.com/t5/i-MX-Processors/I/m-p/655584#M100453 Carlos_Musich 2017-02-21T21:16:14Z