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    <title>i.MX Processors中的主题 Question, i.MX6SoloLite uSDHC</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-uSDHC/m-p/654838#M100304</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about uSDHC of i.MX6SoloLite.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;[Q1]&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The following statements are written in your i.MX6SL reference manual(IMX6SLRM, Rev.2) at the description of SDCLKFS.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;"If setting SDCLKFS and DVS can generate same clock frequency,(For example, in SDR mode, SDCLKFS = 01h is same as DVS = 01h.) SDCLKFS is highly recommended. "&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My customer’s understanding for your recommendation is to use only SDCLKFS than to use both of SDCLKFS and DVS.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could you show me the actual difference between using only SDCLKFS and using both?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Can I understand the value of SDCLKFS should be larger among some combinations of SDCLKFS and DVS values?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;[Q2]&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;After looking at the following thread of i.MX community;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/message/555761"&gt;https://community.nxp.com/message/555761&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My customer thinks that DLL Enable will be automatically adjusted in the case of DLL_CTRL_SLV_OVERRIDE="0" &amp;amp; DLL_CTRL_ENABLE="1".&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is it true?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 21 Feb 2017 06:08:00 GMT</pubDate>
    <dc:creator>Aemj</dc:creator>
    <dc:date>2017-02-21T06:08:00Z</dc:date>
    <item>
      <title>Question, i.MX6SoloLite uSDHC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-uSDHC/m-p/654838#M100304</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about uSDHC of i.MX6SoloLite.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;[Q1]&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The following statements are written in your i.MX6SL reference manual(IMX6SLRM, Rev.2) at the description of SDCLKFS.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;"If setting SDCLKFS and DVS can generate same clock frequency,(For example, in SDR mode, SDCLKFS = 01h is same as DVS = 01h.) SDCLKFS is highly recommended. "&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My customer’s understanding for your recommendation is to use only SDCLKFS than to use both of SDCLKFS and DVS.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could you show me the actual difference between using only SDCLKFS and using both?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Can I understand the value of SDCLKFS should be larger among some combinations of SDCLKFS and DVS values?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;[Q2]&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;After looking at the following thread of i.MX community;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/message/555761"&gt;https://community.nxp.com/message/555761&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My customer thinks that DLL Enable will be automatically adjusted in the case of DLL_CTRL_SLV_OVERRIDE="0" &amp;amp; DLL_CTRL_ENABLE="1".&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is it true?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Feb 2017 06:08:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-uSDHC/m-p/654838#M100304</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2017-02-21T06:08:00Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6SoloLite uSDHC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-uSDHC/m-p/654839#M100305</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Q. My customer’s understanding for your recommendation is to use only SDCLKFS than to use both of SDCLKFS and DVS.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A. Yes, this is correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Q. Could you show me the actual difference between using only SDCLKFS and using both?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A. It is not recommended to use the DVS divider since some (especially odd) settings of this divider can result in non-50% duty cycle card clock.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Q. My customer thinks that DLL Enable will be automatically adjusted in the case of DLL_CTRL_SLV_OVERRIDE="0" &amp;amp; DLL_CTRL_ENABLE="1". Is it true?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A. Yes, this is correct.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 26 Feb 2017 09:18:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6SoloLite-uSDHC/m-p/654839#M100305</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2017-02-26T09:18:15Z</dc:date>
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