Confusing datasheet NAFE33352

InterestedUser — Tue, 06 Oct 2026 14:48:07 GMT

Good day,
my task is to characterize and test the NAFE33352 for potential later use, but have difficulty following or locating some information in the following datasheet. https://www.nxp.com/docs/en/data-sheet/NAFE33352.pdf
Until now, after just glancing over the most important functionalities, I have the following problems/questions in no specific order:

a) 7.6.3 HV Input:
For single-ended analog measurements the datasheet says to configure the LVMUX like this:
HV input positive: AI1P, Isense
HV input positive: AI1N, Vsense

I can't find those configurations in Table 12. With a bit of fantasy, the first could be 00010/b, assuming Vsense is VSNS. But the second combination doesn't seem to exist. Even if they existed, do I just have to tie the three SENSE pins down to GND?
How else can I measure AI1P and AI1N vs GND? I need two single-ended channels for my application.

b) 7.6.6 Analog inputs to low-voltage multiplexer (LV_MUX)
Table 12, what is VCM? The COM input of the MUX seen in Figure 1? Is the COM the common mode output level for the differential PGAs? Can I use COM as reference for my single-ended measurements?

c) 5 Block diagram
Why are there 2 LS inputs per MUX and what do the mean? How can the outputs of the AMPs of DAC and VSENSE be connected together?

d) 7.5.8 Voltage sources polarity switching (AC excitation)
What happened to VIEX_CHOP? It's only mentioned twice in this section but never where to find it and in which register to set it.

e) 7.14 CMD_MM, multichannel multireading command
How do I configure the respective registers, which channels can I choose from? Does this chip not only have a 2-channel ADC? Where can I find the CH_CONFIGx registers that are mentioned in the section?
Also Table 20 mentions DATA0...DATA7 for up to 8 channels but no more information what this means? Are the combinations of Table 12 considered channels?

It may be that some information I'm looking for is somewhere in the datasheet, but even if that is the case, it is well hidden or a different terminology/abbreviation is used, which makes it even more confusing and hard to find.
If I want to use this IC, I would need to order an eval-board as soon as possible, but I can't with so many open questions and not knowing if it's even possible to do what I try to do with the chip. In a nutshell, one analog input and 2 independent analog input channels.
Hoping to hear from you soon. Best regards,
Lukas

Re: Confusing datasheet NAFE33352

ErikaC — Wed, 07 Oct 2026 20:27:48 GMT

Hello,

a) AI1P and AI1N can be used as two independent single-ended inputs (IN_SEL = 00100 and 00101). Connect the external signal return to AGND. They share the same ADC, so measurements are sequential. The valid configurations are:

b)VCM and COM are internal signals, not external reference pins. For single-ended measurements, connect the signal return to AGND.

c)The two LS blocks are internal level shifters for the positive and negative MUX paths. They do not represent additional external inputs.

d) The polarity-chopping function is configured through AIO_CHOP[7:6] in AI_CONFIG2 (0x22). Set AIO_CHOP = 11b for DAC polarity chopping with two averaged ADC readings.

e) The device supports 8 logical channels (CH0–CH7) sharing the same ADC. Each logical channel can have its own input and ADC configuration, is enabled through AI_MULTI_CH_EN, and has a corresponding AI_DATA0–AI_DATA7 result register.

Hope this helps!

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Confusing datasheet NAFE33352

Re: Confusing datasheet NAFE33352