<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: QTimer input edge interrupt input filter on DSC MC56F8037 in Digital Signal Controllers</title>
    <link>https://community.nxp.com/t5/Digital-Signal-Controllers/QTimer-input-edge-interrupt-input-filter-on-DSC-MC56F8037/m-p/282188#M67</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Tazio, I don't know how you found the filter didn't work, but it should be working per you configuration. You can enable the capture interrupt and toggle a GPIO in the ISR. Observe the time between the edges of triggering input signal and the output of that GPIO, it should change as the configured latency changes.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 28 Feb 2014 06:42:43 GMT</pubDate>
    <dc:creator>sutter_zhou</dc:creator>
    <dc:date>2014-02-28T06:42:43Z</dc:date>
    <item>
      <title>QTimer input edge interrupt input filter on DSC MC56F8037</title>
      <link>https://community.nxp.com/t5/Digital-Signal-Controllers/QTimer-input-edge-interrupt-input-filter-on-DSC-MC56F8037/m-p/282187#M66</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dars Sirs,&lt;/P&gt;&lt;P&gt;in my application i use an MC56F8037 DSC.&lt;/P&gt;&lt;P&gt;I am using input edges of secondary input external pin of Quad Timers as source of interrupts.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have noticed that the input filter is not working.&lt;/P&gt;&lt;P&gt;In fact i don't see any effect on the latency by changing the sampling period and consecutive samples requid to agree parameters.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is it the expected behaviour of this filter?&lt;BR /&gt;Is the interrupt working on raw signal?&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards and thank you in advance&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Tazio &lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;P.S: the Timer is configured as follows:&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; QT_A2 Configuration&lt;BR /&gt;--------------------------------------------&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Count mode: Counting mode, count rising edges of primary source &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Timer Channel Enabled (counter starts counting immediatelly after initialized): Yes&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Primary source: Prescaler (IPB clock/ 32) , Secondary: Counter #1 input pin &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Input polarity: True , Output polarity: True &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Input capture mode: Load capture register on both edges of secondary input &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Output mode: Asserted while counter is active &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Count stop mode: Count repeatedly , Count length: Roll over , Count direction: Count up &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Output enable (OFLAG to pin): No &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Force OFLAG output at startup: No , Forced OFLAG value: 0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Master mode (broadcast compare event): Disable&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Enable external OFLAG force (on broadcasted event): No &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Co-channel initialization (on broadcasted event): No &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Preload Control: 1: Never , Load Reg: 0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 2: Never , Load Reg: 0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Interrupts: Overflow: Enabled &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Input edge: Enabled &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Compare: Disabled&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Cmp 1: Disabled&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Cmp 2: Disabled&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Input Filter: Input Signal Sampling [timer clocks] : 96&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Consecutive Samples Required to Agree: 10 &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Input Signal Latency: 30.0625 us&lt;BR /&gt;.*/&lt;BR /&gt;#define QT_A2_CTRL_INIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x3A80U&lt;BR /&gt;#define QT_A2_SCR_INIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x14C0U&lt;BR /&gt;#define QT_A2_CMP1_INIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xFFDCU&lt;BR /&gt;#define QT_A2_FILT_INIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0760U&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Feb 2014 13:07:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Digital-Signal-Controllers/QTimer-input-edge-interrupt-input-filter-on-DSC-MC56F8037/m-p/282187#M66</guid>
      <dc:creator>Tazio</dc:creator>
      <dc:date>2014-02-06T13:07:35Z</dc:date>
    </item>
    <item>
      <title>Re: QTimer input edge interrupt input filter on DSC MC56F8037</title>
      <link>https://community.nxp.com/t5/Digital-Signal-Controllers/QTimer-input-edge-interrupt-input-filter-on-DSC-MC56F8037/m-p/282188#M67</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Tazio, I don't know how you found the filter didn't work, but it should be working per you configuration. You can enable the capture interrupt and toggle a GPIO in the ISR. Observe the time between the edges of triggering input signal and the output of that GPIO, it should change as the configured latency changes.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Feb 2014 06:42:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Digital-Signal-Controllers/QTimer-input-edge-interrupt-input-filter-on-DSC-MC56F8037/m-p/282188#M67</guid>
      <dc:creator>sutter_zhou</dc:creator>
      <dc:date>2014-02-28T06:42:43Z</dc:date>
    </item>
  </channel>
</rss>

