Digital Signal ControllersのトピックThis documents the required initialization sequence for the MC56F8400 series eFlexPWM with micro-edge https://community.nxp.com/t5/Digital-Signal-Controllers/This-documents-the-required-initialization-sequence-for-the/m-p/426277#M546 <HTML><HEAD></HEAD><BODY><P><STRONG><SPAN style="color: #3d3d3d;">Announcement</SPAN>:</STRONG></P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>When using the fractional edge delay on the eFlexPWM, there is the requirement to not program pulses narrower than 3 clock cycles. </P><P>This requirement is only for channels using the fractional edge delay and does not apply to channels that are capable of fractional delay but not using the fractional delay.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>PWM outputs <STRONG>may</STRONG>&nbsp; on <STRONG>some</STRONG> units power up to a logic 1 state when the analog micro-edge placer block is used.&nbsp; This is unavoidable and per the design.&nbsp; It is not a defect.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P><STRONG>To get proper initialization</STRONG> when using the analog micro-edge placer block in the PWM, it is required power it up and run at least one PWM period where there is a PWM edge transition before enabling the PWM outputs.&nbsp; This will ensure that the PWM outputs are in a known state and allow the device to operate normally.</P></BODY></HTML> Wed, 03 Jun 2015 18:04:06 GMT johnlwinters 2015-06-03T18:04:06Z This documents the required initialization sequence for the MC56F8400 series eFlexPWM with micro-edge https://community.nxp.com/t5/Digital-Signal-Controllers/This-documents-the-required-initialization-sequence-for-the/m-p/426277#M546 <HTML><HEAD></HEAD><BODY><P><STRONG><SPAN style="color: #3d3d3d;">Announcement</SPAN>:</STRONG></P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>When using the fractional edge delay on the eFlexPWM, there is the requirement to not program pulses narrower than 3 clock cycles. </P><P>This requirement is only for channels using the fractional edge delay and does not apply to channels that are capable of fractional delay but not using the fractional delay.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>PWM outputs <STRONG>may</STRONG>&nbsp; on <STRONG>some</STRONG> units power up to a logic 1 state when the analog micro-edge placer block is used.&nbsp; This is unavoidable and per the design.&nbsp; It is not a defect.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P><STRONG>To get proper initialization</STRONG> when using the analog micro-edge placer block in the PWM, it is required power it up and run at least one PWM period where there is a PWM edge transition before enabling the PWM outputs.&nbsp; This will ensure that the PWM outputs are in a known state and allow the device to operate normally.</P></BODY></HTML> Wed, 03 Jun 2015 18:04:06 GMT https://community.nxp.com/t5/Digital-Signal-Controllers/This-documents-the-required-initialization-sequence-for-the/m-p/426277#M546 johnlwinters 2015-06-03T18:04:06Z