topic Re: Clock generation in CAN bus devices in Digital Signal Controllers

Clock generation in CAN bus devices

rknispel — Thu, 14 Jul 2022 13:45:10 GMT

I am looking for details of the clock generation in UJA1169ATK/F:

clock source
PLL
Jitter in 13 bit interval of CAN communications

Is there a technology papaer where it can be derived from?

Re: Clock generation in CAN bus devices

rknispel — Fri, 15 Jul 2022 10:07:13 GMT

The data sheet says "microcontrollerindependent clock source" is present on the chip, but where can further details be taken from?

Re: Clock generation in CAN bus devices

guoweisun — Mon, 18 Jul 2022 00:10:40 GMT

What kinds of clock detail information do you need?

Re: Clock generation in CAN bus devices

rknispel — Mon, 18 Jul 2022 10:32:55 GMT

My questionnaire is about details of the Automotive qualification of the CAN communications of UJA1169ATK/F:

CAN network clock source
PLL frequency [MHz]
max. PLL jitter in 13 bit interval
oscillator manufacturer
oscillator part name
oscillator frequency [MHz]
oscillator tolerance [%]

Possible answers include clock recovery from CANH/CANL lines, and the oscillator would be MCU oscillator.

Re: Clock generation in CAN bus devices

guoweisun — Fri, 22 Jul 2022 06:55:07 GMT

These parameters should be checked or setting in CAN controller side,right?UJA1169 is CAN transceiver.

Re: Clock generation in CAN bus devices

rknispel — Fri, 22 Jul 2022 09:49:48 GMT

The parameters are relevant for reliabilty of CAN communications in on-board network as Automotive application. UJA1169 is considered for SBC of such a component.

Typically the internal clock is generated from TXD by clock recovery. I am looking for more details on this process!

Help is very much appreciated and thanks for any hints in advance!

Re: Clock generation in CAN bus devices

rknispel — Tue, 26 Jul 2022 09:25:45 GMT

The question was transferred into a service case and resolved there.