Digital Signal ControllersのトピックRe: two TMRs and two TMR interrupt configuration

two TMRs and two TMR interrupt configuration

terrybogard — Tue, 09 Nov 2021 02:06:40 GMT

Dear NXP expert,

I set TMR1 20kHz and enable the TMR1 interrupt, and TMR1 2kHz and enable the TMR2 interrupt. Both TMR1 and TMR2 interrupt, the ADC will be triggered, at the end of ADC sample, ADC ISR will run. is it OK about this configuration?

Re: two TMRs and two TMR interrupt configuration

xiangjun_rong — Tue, 09 Nov 2021 05:37:23 GMT

Hi,

I suppose that your scheme is okay, but you have to add the #pragma interrupt on at the beginning of the ISR, and #pragma interrupt off at the end of ISR for each ISR function.

Hope it can help you

#pragma interrupt on
void MC56F827xx_ISR_SCI1_Transmitter(void)
{
if(QSCI1_STAT&0x8000)
{
QSCI1_DATA='C';
}
}

#pragma interrupt off

Re: two TMRs and two TMR interrupt configuration

terrybogard — Tue, 09 Nov 2021 05:45:30 GMT

xiangjun,

#pragma is necessary? and what's the reason about that? thanks.

Re: two TMRs and two TMR interrupt configuration

xiangjun_rong — Tue, 09 Nov 2021 07:01:40 GMT

Hi, Terry,

using "#pragma interrupt on" tells the compiler to generate "rti" rather than "rts" at the end of function code. The "rti" is return from ISR. The "rts" is return from general api function.

Hope it can help you

XiangJun Rong

Re: two TMRs and two TMR interrupt configuration

terrybogard — Tue, 07 Dec 2021 09:12:40 GMT

Hi xiangjun,

if ISR return RTS, what will happen? MCU will do what difference about RTI and RTS?

Thanks

Re: two TMRs and two TMR interrupt configuration

xiangjun_rong — Wed, 08 Dec 2021 02:01:25 GMT

Hi,

As you know that the ISR uses rti, general subroutine uses rts. The RTI will pop both PC and SR(status register), but the RTS just will pop PC automatically.

When the DSC enters ISR, it push both PC and SR automatically, so when exits ISR, it must pop both PC and SR using rti.

Hope it can help you

XiangJun Rong

Re: two TMRs and two TMR interrupt configuration

cotaxak207 — Sat, 08 Jan 2022 06:14:31 GMT

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