Reading the Status Reg (SR)

jimb2 — Wed, 10 Dec 2014 17:38:50 GMT

I'm trying to read the status reg (SR) of the DSP56800E "8365" device but I always read I1 & I0 as 1 (intr masked). I have a routine that operates on shared memory so I want to disable intr only if they are not already disabled by the calling function. If I read the SR into Y0 reg, it always shows intr masked even after I explicitly execute a "bfclr #0x0300,SR" asm insn. I've also looked at the SR reg that is stacked upon a function call and see the same thing.

The spec says those I1 & I0 bits are R/W and it doesn't show that should always read 1, so what am I doing wrong?

Re: Reading the Status Reg (SR)

xiangjun_rong — Fri, 12 Dec 2014 06:57:45 GMT

I think you can clear the I0/I1 bit of SR with the following code:

asm(bfclr #$0300, SR); //enable interrupt

you can set the I0/I1 bit in SR with the following code

asm(bfset #$0300, SR); //disable interrupt

if you want to jump based on the condition of SR, you can use the code Jcc or Bcc instruction.

xiangjun Rong

topic Re: Reading the Status Reg (SR) in Digital Signal Controllers

Reading the Status Reg (SR)

Re: Reading the Status Reg (SR)