56F807, PFIU_CNTL & PFIU2_CNTL, Processor Expert

j___ — Sun, 23 Sep 2018 12:40:00 GMT

I am trying to erase\program flash on the 56F807. I have found that the application flash is comprised of two 32K flash modules (with some of the address space removed for boot flash & misc).

Using CodeWarrior 8.3 with Processor Expert, i generated the flash programming code. In that code there are 2 #defines that provide the register set base addresses:

#define PFIU_CNTL_ASM X:4928 //For top 32k of app flash

#define PFIU2_CNTL_ASM X:5152 //For bottom 24k of app flash

also there are:

#define PROG_FLASH_END 32767 //For top 32k of app flash

#define PROG_FLASH2_END 61439 //For bottom 24k of app flash

See "DSP56F800 Family User’s Manual, Rev. 8", page 3-12, for details on these base values.

The Processor Expert project is attached to this post.

The IFsh_app_2.c file in the attached example uses the PFIU2 registers EXCEPT when the actual word programming is done. For that final step, it calls:

IFsh_app_1_WIR_routine(address, Data); /* Process routine in RAM.

This routine uses PFIU_CNTL_ASM only, which is the base address for PFIU_CTRL, not the PFIU2_CTRL !!!

Why is this?

I have looked through the documentation and have not found the description that states to use PFIU_CTRL when programming the PFIU2 flash module. It's probably there somewhere, but I haven't found this explanation in the documentation and I want to avoid issues as I am near the end of my deadline when I found this.

I have run into a lot of bugs & issues using these over-priced, old, unreliable, un-maintained, CodeWarrior tools. I have to be proactive and understand this to prevent a potential issue.

All I really need is to see where, in the documentation, it describes to use PFIU_CNTL for status when programming the PFIU2 flash module.

If it is not in the documentation, then can someone provide a rationale or experience for why this could\should work?

Re: 56F807, PFIU_CNTL & PFIU2_CNTL, Processor Expert

xiangjun_rong — Tue, 25 Sep 2018 07:43:54 GMT

Hi, Jim,

I think it is a bug of the PE, it should be check the BUSY bit in PFIU2_CNTL register instead of PFIU2_CNTL if you program the second program flash from P:0x8000.

As you know that DSP56F807 is very old, the PE was developed later, the PE code is not test fully.

Hope it can help you

Xiangjun Rong

topic 56F807, PFIU_CNTL & PFIU2_CNTL, Processor Expert in Digital Signal Controllers

56F807, PFIU_CNTL & PFIU2_CNTL, Processor Expert

Re: 56F807, PFIU_CNTL & PFIU2_CNTL, Processor Expert