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    <title>topic Re: HCS08 C: bit field optimization in CodeWarrior for MCU</title>
    <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/HCS08-C-bit-field-optimization/m-p/196146#M7246</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;I believe that the order of evaluation of nested assignments isn't specified by ISO C. So the compiler is free to evaluate the nested assignment in a completely random order, which might give code that isn't possible to optimize.&lt;BR /&gt;&lt;BR /&gt;Another explanation could be that since there is no situation where it is motivated to use nested assignments, perhaps CW doesn't even bother with optimizing them.&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 26 Feb 2008 15:51:47 GMT</pubDate>
    <dc:creator>Lundin</dc:creator>
    <dc:date>2008-02-26T15:51:47Z</dc:date>
    <item>
      <title>HCS08 C: bit field optimization</title>
      <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/HCS08-C-bit-field-optimization/m-p/196145#M7245</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I defined LCD segments as bits in a struct.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;typedef struct{ unsigned char R0:1; unsigned char R1:1; unsigned char R2:1; unsigned char R3:1; unsigned char R4:1; unsigned char R5:1; unsigned char R6:1; unsigned char R7:1;} TBits;typedef union { unsigned char Val; TBits Bit;} TLcdByte;&lt;/PRE&gt;&lt;PRE&gt;&lt;/PRE&gt;&lt;PRE&gt;#pragma DATA_SEG MY_ZEROPAGE
&amp;nbsp; TLcdByte LCD_RAM[20];&lt;/PRE&gt;&lt;/DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;and the definitions:&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;#define IND_L1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[10].Bit.R0#define IND_L2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[14].Bit.R2#define IND_L3&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[14].Bit.R3#define IND_NL1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[10].Bit.R2#define IND_NL2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[14].Bit.R0#define IND_NL3&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[14].Bit.R1#define IND_T1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[14].Bit.R5#define IND_T2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[14].Bit.R7#define IND_T3&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[9].Bit.R4#define IND_T4&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LCD_RAM[8].Bit.R4&lt;/PRE&gt;&lt;PRE&gt;...&lt;/PRE&gt;&lt;/DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;If I use&lt;/DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt; IND_NL1 = 0; IND_NL2 = 0; IND_NL3 = 0; IND_L1 = 0; IND_L2 = 0; IND_L3 = 0; IND_PP = 0; IND_NP = 0; IND_PQ = 0; IND_NQ = 0;&lt;/PRE&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;instead of&lt;/P&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;IND_NL1 = IND_NL2 = IND_NL3 = IND_L1 = IND_L2 = IND_L3 = IND_PP = IND_NP = IND_PQ = IND_NQ = 0;&lt;/PRE&gt;&lt;/DIV&gt;&lt;P&gt;it generates more optimal code. Is this normal?&lt;/P&gt;&lt;P&gt;CW v6.1&lt;/P&gt;&lt;P&gt;10x&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;/P&gt;&lt;DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Oct 2020 09:51:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/CodeWarrior-for-MCU/HCS08-C-bit-field-optimization/m-p/196145#M7245</guid>
      <dc:creator>BasePointer</dc:creator>
      <dc:date>2020-10-29T09:51:28Z</dc:date>
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    <item>
      <title>Re: HCS08 C: bit field optimization</title>
      <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/HCS08-C-bit-field-optimization/m-p/196146#M7246</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;I believe that the order of evaluation of nested assignments isn't specified by ISO C. So the compiler is free to evaluate the nested assignment in a completely random order, which might give code that isn't possible to optimize.&lt;BR /&gt;&lt;BR /&gt;Another explanation could be that since there is no situation where it is motivated to use nested assignments, perhaps CW doesn't even bother with optimizing them.&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Feb 2008 15:51:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/CodeWarrior-for-MCU/HCS08-C-bit-field-optimization/m-p/196146#M7246</guid>
      <dc:creator>Lundin</dc:creator>
      <dc:date>2008-02-26T15:51:47Z</dc:date>
    </item>
    <item>
      <title>Re: HCS08 C: bit field optimization</title>
      <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/HCS08-C-bit-field-optimization/m-p/196147#M7247</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Bad compiler.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thanks Lundin.&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Feb 2008 17:28:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/CodeWarrior-for-MCU/HCS08-C-bit-field-optimization/m-p/196147#M7247</guid>
      <dc:creator>BasePointer</dc:creator>
      <dc:date>2008-02-26T17:28:42Z</dc:date>
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