topic Re: Banked memory model in CodeWarrior for MCU

Banked memory model

SofTA — Sat, 30 May 2009 07:23:16 GMT

Hi Expert,

I use CW and PE to build my project. My current project uses small memory model. It seems I run out of the memory because I got en error message as "Out of allocation space in seqment ROM at address 0X7EE8". So, I re-started a project with banked memory model and imported all of the code to the new project. But it seems the new project with banked memory model can not hold even my origianl code. It gave me the same error message on the code that works on the small memory model. If I remove some code, then it can pass. What is my problem? Is there any trick to set up the banked memory model with PE?

Thanks a lot.

Softa

Re: Banked memory model

CompilerGuru — Mon, 01 Jun 2009 05:34:59 GMT

Please provide more details.

Especially which derivative and architecture you are using (S08, HC12, S12, S12X)?

Check the map file to see which memory area are, and which are not used.

Daniel

Re: Banked memory model

SofTA — Mon, 01 Jun 2009 23:33:32 GMT

Hi CompilerGuru,

Thank you very much for offering help. I am not a professional programmer but an electrical engineer knowing enough C programming to get my job done. So, I may miss something that is rudimentary to a professional.

The chip I am using is MC9S08QE128CLK. Besides setting the memory model as banked (and I checked Build option in CPU bean that all of the memory areas are enabled), I did have tried to put _far modifier in front of some functions (e.g. void __far DSP(void)) which has no effect. Following is part of the Project.map file. I am not sure if it can give you some hint?

Look forward hearing from you and many many thanks.

Softa

Project.map file:

*********************************************************************************************
LINKING FAILED
The linking process failed in some stage.
Depending on the phase the linker failed, part of the information contained in this map file may be inaccurate or wrong.
If the linking failed before the allocation phase finished, then the addresses might be inaccurate.
Also summary information like the code size is likely to be misleading.
---------------------------------------------------------------------------------------------

*********************************************************************************************
TARGET SECTION
---------------------------------------------------------------------------------------------
Processor : Freescale HC08
Memory Model: BANKED
File Format : ELF (no debug info)
Linker : SmartLinker V-5.0.37 Build 9092, Apr 3 2009

*********************************************************************************************
FILE SECTION
---------------------------------------------------------------------------------------------
RTSHC08.C.o (ansibim.lib)               Model: BANKED,        Lang: ANSI-C
STDLIB.C.o (ansibim.lib)                Model: BANKED,        Lang: ANSI-C
Start08.c.o                             Model: BANKED,        Lang: ANSI-C
Cpu.c.o                                 Model: BANKED,        Lang: ANSI-C
IO_Map.c.o                              Model: BANKED,        Lang: ANSI-C
Vectors.c.o                             Model: BANKED,        Lang: ANSI-C
…
…
…
*********************************************************************************************
STARTUP SECTION
---------------------------------------------------------------------------------------------

*********************************************************************************************
SECTION-ALLOCATION SECTION
Section Name                    Size Type     From       To       Segment
---------------------------------------------------------------------------------------------
NON_BANKED                      1865     R     0x20F1     0x2839   ROM
.text                          19375     R     0x283A     0x73E8   ROM
.rodata                           44     R     0x73E9     0x7414   ROM
.rodata1                        1358     R     0x7415     0x7962   ROM
.abs_section_ffbd                  1     R     0xFFBD     0xFFBD   .absSeg0
.abs_section_ffbf                  1     R     0xFFBF     0xFFBF   .absSeg1
.abs_section_0                     1   N/I        0x0        0x0   .absSeg2
.abs_section_1                     1   N/I        0x1        0x1   .absSeg3
….
…
…
abs_section_1870                  2   N/I     0x1870     0x1871   .absSeg181
.abs_section_ffc0                 64     R     0xFFC0     0xFFFF   .absSeg182
.abs_section_8000                512   N/I     0x8000     0x81FF   .absSeg183
.bss                             839   R/W       0xA0      0x3E6   RAM
.startData                        18     R     0x20DF     0x20F0   ROM
.init                             95     R     0x2080     0x20DE   ROM
.common                         1384   R/W      0x3E7      0x94E   RAM
AS1_CODE                         271     R     0x7963     0x7A71   ROM
AS2_CODE                         283     R     0x7A72     0x7B8C   ROM
SM1_CODE                          84     R     0x7B8D     0x7BE0   ROM
SM2_CODE                          26     R     0x7BE1     0x7BFA   ROM
…
…
…
.stack                           128   R/W      0x94F      0x9CE   RAM

Summary of section sizes per section type:
READ_ONLY (R):        5EAA (dec:    24234)
READ_WRITE (R/W):      92F (dec:     2351)
NO_INIT (N/I):         2CF (dec:      719)

Re: Banked memory model

CompilerGuru — Thu, 29 Oct 2020 09:37:06 GMT

Not sure how complete PE supports the banked memory model. It looks like processor expert is generating the map file for the banked memory model just as for the small memory model. And more importantly, it does not allocate its interrupt handlers explicitly non banked as it is necessary to place DEFAULT_ROM into banks.

So I would suggest to stick with the small memory model and to place the own custom functions into the banked areas. See below how this can be done. Note that the code below will place the sample functions into the banked memory regardless of the memory model.

Maybe some PE expert can guide us how to setup the banked memory model with PE so that by default the code ends up paged.

Adding a __far qualifier does change the calling convention of the function. As the functions have to be allocated differently as well, using a pragma as below is necessary anyway. By using the __FAR_SEG section qualifier, the __far is not necessary at all. In all but advanced special cases, declaring individual functions with __far is not necessary.

Daniel

sample.h:

#ifndef SAMPLE_H_
#define SAMPLE_H_

#pragma push
#pragma CODE_SEG __FAR_SEG PAGED_ROM

extern void SampleFunction0(void);
extern void SampleFunction1(void);
extern void SampleFunction2(void);

#pragma pop

#endif // SAMPLE_H_

sample.c:

#include "sample.h"#pragma push#pragma CODE_SEG __FAR_SEG PAGED_ROMvoid SampleFunction0() {}  void SampleFunction1() {  SampleFunction0(); }void SampleFunction2() {  SampleFunction1(); }#pragma pop

Re: Banked memory model

SofTA — Wed, 03 Jun 2009 03:26:33 GMT

Hi Daniel,

Your suggestion worked as magic. Thank you very much for the help.

Have a great day!

Softa

Re: Banked memory model

Ricardo_RauppV — Wed, 09 Sep 2009 18:37:06 GMT

Hi guys

I have some doubts about it ( I´m using a QE128):

1- If I have a 70Kb code, shoud I use small memory model and just tell the compiler to put some extra code in paged memory bu using CODE_SEG pragmas?or shoul I remake the whole project as banked..?

2- Allocatoing a code using CODE_SEG pragma, I don´t need to add the far word in each function of this segment, is it? ( I preffer just use simp,e prgma to entirte file instead of each new funcion must remember to add far word..probably I will forget it sometimes...)

3- is there some complete (inerruption use,different segments code area,prm file,etc) source code I could take a look to help me to implement my application?

Thanks !!

Ricardo Raupp

Re: Banked memory model

CompilerGuru — Thu, 10 Sep 2009 00:20:11 GMT

The banked memory model sounds appropriate, the overhead of the banking call exists but is not as significant as for data paging. However placing some of your code explicitely into a is also simple and a bit more efficient than using the banked memory model.

Use a

#pragma CODE_SEG __FAR_SEG YOUR_BANKED_SECTION_NAME

to specify that functions in this section should use the __far calling convention, also note that functions have to be declared and defined in this section, say the header file should contain the same #pragma (and a #pragma DEFAULT at the end).

Using the __far for functions is rarely necessary, it makes sence for singular cases only where the location a function gets placed does not match the calling convention to be used.

Sorry, no simple sample from me. Clicking a sample application together with Processor Expert is an alternative to see one way things can be done.

Daniel

Re: Banked memory model

cartoon — Tue, 20 Oct 2009 10:27:09 GMT

Hi CmpilerGuru,

I use CW6.2 & PE. The chip is MC9S08QE128. I used banked memory model putting the interrupts to non-banked like this. Because my code size is 90kb.

#ifndef __SMALL__
#pragma CODE_SEG __NEAR_SEG NON_BANKED
#endif

Interrupt void()

#ifndef __SMALL__
#pragma CODE_SEG DEFAULT
#endif

I'm ok with this one. But after all, I found timing is a bit slow.. Because I need the faster timing,

then I created a new project with the small memory model by putting all the function calls to banked area as suggested in this post like this (for example).

/*
* File: mdrv_eeprom.h
*
*/

/*** BeginHeader */
#ifndef __MDRV_EEPROM_H__
#define __MDRV_EEPROM_H__
/*** EndHeader */

#pragma push
#pragma CODE_SEG __FAR_SEG PAGED_ROM

//***** Functions *****
extern void eeprom_read(unsigned char * dest, unsigned long addr, unsigned short len);
extern void eeprom_write(unsigned long addr, unsigned char * src, unsigned short len);

#pragma pop
/*** BeginHeader */
#endif __MDRV_EEPROM_H__
/*** EndHeader */

/*** BeginHeader */
#ifndef __MDRV_EEPROM_C__
#define __MDRV_EEPROM_C__
/*** EndHeader */

#include "mdrv_acu205.h"

/////////////////////////////////////
// Begin of Functions
/////////////////////////////////////
#pragma push
#pragma CODE_SEG __FAR_SEG PAGED_ROM

void eeprom_read(unsigned char * dest, unsigned long addr, unsigned short len)
{

}

void eeprom_write(unsigned long addr, unsigned char * src, unsigned short len)
{

}

#pragma pop

/*** BeginHeader */
#endif __MDRV_EEPROM_C__
/*** EndHeader */

But now I found that in P&E debugging, mcu frequencies changed to different frequencies. What am I wrong? Pls suggest me something. I do appreciate your suggestion.

Looking forwards to your reply.

Regards,