topic Re: ADC conversion completion interrupt in MC56F83789 controller in CodeWarrior for MCU

ADC conversion completion interrupt in MC56F83789 controller

Aman786 — Tue, 11 Jun 2024 04:54:11 GMT

Hi,

I was trying to schedule ADC conversion complete interrupt for ADC which is triggered by PWM pulse of 50KHZ, but I noticed the interrupt executed only at 25KHz instead of 50. Can you please let me know the reason and how to correct it?

@xiangjun_rong

Re: ADC conversion completion interrupt in MC56F83789 controller

xiangjun_rong — Thu, 13 Jun 2024 06:22:12 GMT

Hi,

Do you use software triggering or hardware triggering?

If you use software triggering mode, you configured to have reloading event to fire interrupt, in the reloading ISR, you set the ADC SRART bit to launch a ADC conversion. In the process, The SMxCTRL[LDFQ] controls the frequency, if you want to trigger ADC for each PWM, set the LDFQ=0.

If you use hardware triggering mode, for example, the PWM generates triggering signal via SMxTCTRL register, then the signal triggers ADC via cross-bar.

Pls refer to 27.3.22 Output Trigger Control Register (SM0TCTRL - SM3T
CTRL). If you use hardware triggering mode and want to trigger ADC for each PWM cycle, I suggest you clear the SMxTCTRL[TRGFRQ] bit, otherwise, the LDFQ also controls the triggering frequency.

If you toggle a GPIO in ADC ISR, note if the PWM is 50khz, the GPIO frequency is 25Khz when each PWM cycle triggers ADC.

Hope it can help you

XiangJun Rong

Re: ADC conversion completion interrupt in MC56F83789 controller

Aman786 — Fri, 14 Jun 2024 03:48:43 GMT

Thanks @xiangjun_rong for the reply.

I was using hardware interrupt trigger using the PWM however I checked the ADC scanning configuration there were some corrections required in the configuration .Once done with correct configuration this interrupt started triggering at 50KHz frequency.

Regarding the interrupts, I have an additional question.

00 IRQ disabled (default)
01 IRQ Priority Level 0
10 IRQ Priority Level 1
11 IRQ Priority Level 2

This controller has 3 interrupt levels 0-2, so if have more than 3 interrupts how interrupts can be configured. If the same priority comes for the interrupts, then how the controller behaves?

Re: ADC conversion completion interrupt in MC56F83789 controller

xiangjun_rong — Fri, 14 Jun 2024 05:37:06 GMT

Hi,

What you said is correct:

00 IRQ disabled (default)
01 IRQ Priority Level 0
10 IRQ Priority Level 1
11 IRQ Priority Level 2

The level 3 is non-maskable interrupt, the highest priority.

Regarding the interrupt priority mechanism, pls refer to 9.3.1 Interrupt Priority Structure in the attached family manual of DSC.

Hope it can help you

XiangJun Rong

Re: ADC conversion completion interrupt in MC56F83789 controller

xiangjun_rong — Fri, 14 Jun 2024 05:46:49 GMT

Hi,

You can download the DSC family manual from the website:

DSP56800E and DSP56800EX - Reference Manual

https://www.nxp.com/products/processors-and-microcontrollers/additional-mpu-mcus-architectures/digital-signal-controllers/32-bit-56800ex-ef-core/performance-level-digital-signal-controllers-usb-fs-otg-can-fd:MC56F83xxx

Hope it can help you

XiangJun Rong

Re: ADC conversion completion interrupt in MC56F83789 controller

Aman786 — Fri, 14 Jun 2024 09:29:14 GMT

Thanks @xiangjun_rong .

There is one more clarification required. Reg DSC controller, is it possible to control PFC and DC_DC using a single controller?