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    <title>CodeWarrior for MCU中的主题 Re: FSICE for HC08 and interrupt vectors for True-Time Simulator</title>
    <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134440#M1582</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Hello, sorry for big delay&amp;nbsp;with my&amp;nbsp;answer ...&lt;/DIV&gt;&lt;DIV&gt;I'm targeting GZ32 mc using FSICE (btw, the file .mem for 32K emulation chip [MCUID 043B], wasn't available in prog\mem directory, I had to create, instead 16K and 48K .mem files&amp;nbsp;&amp;nbsp;are available, why ... ?).&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;The problem is in the prm file, below pieces of sorces :&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;U&gt;FROM CODE:&lt;/U&gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;U&gt;&lt;/U&gt;&lt;/STRONG&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;#define vjmp&amp;nbsp; 0xcc&amp;nbsp;// JUMP opcode&lt;/DIV&gt;&lt;DIV&gt;typedef struct&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;char opcode;&lt;BR /&gt;&amp;nbsp;void (* const _vectab)();&lt;BR /&gt;} tIntJmpTable;&lt;/DIV&gt;&lt;DIV&gt;#pragma CONST_SEG APPLVECT&lt;BR /&gt;const tIntJmpTable ApplIntJmpTable[22] =&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* msCAN Transmit */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, CanRxIntpt,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* msCAN Receive */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, CanErrorIntpt,&amp;nbsp;&amp;nbsp;&amp;nbsp;/* msCAN Error */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, CanWakeUpIntpt,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* msCAN Wakeup */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Timbase */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, AdcIntp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* ADC */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, KeyIntp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;/* Keyboard */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp; &amp;nbsp;/* SCI Transmit */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* SCI Receive */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* SCI Error */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* SPI Transmit */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* SPI Receive */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp;&amp;nbsp;/* TIM2 Overflow */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, Tim2CH1Intp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* TIM2 CH1 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, Tim2CH0Intp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* TIM2 CH0 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, Tim1OverIntp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* TIM1 Overflow */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* TIM1 CH1 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp;&amp;nbsp;/* TIM1 CH0 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* PLL */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp;&amp;nbsp;/* IRQ1 vector handler */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, ResetIntpt,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, ResetIntpt,&lt;BR /&gt;};&lt;BR /&gt;#pragma CONST_SEG DEFAULT&lt;/DIV&gt;&lt;DIV&gt;----------------------------------------------------------------------&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;U&gt;PRM FILE:&lt;/U&gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;U&gt;&lt;/U&gt;&lt;/STRONG&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;NAMES END&lt;/DIV&gt;&lt;DIV&gt;SECTIONS&lt;BR /&gt;...&lt;BR /&gt;&amp;nbsp;AVECT &amp;nbsp;&amp;nbsp;= READ_ONLY &amp;nbsp;&lt;STRONG&gt;0xE800 TO 0xE87F&lt;/STRONG&gt;;&lt;BR /&gt;...&lt;BR /&gt;END&lt;/DIV&gt;&lt;DIV&gt;PLACEMENT&amp;nbsp;&amp;nbsp;&lt;BR /&gt;...&lt;BR /&gt;&amp;nbsp;APPLVECT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; INTO&amp;nbsp; AVECT;&lt;BR /&gt;...&lt;BR /&gt;END&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;At the beginning I didn't check prm file but it's clear that AVECT section didn't point to correct area where interrupts source&amp;nbsp;are&amp;nbsp;located (FFD4-FFFF), indeed at address 0xE82A there is Tim2CH0Intp vector address (instead to FFF0) ...&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;It doesn't seem to me that interrupt vectors can be relocated so I'm not able to understand how it's possible that mc could run well&amp;nbsp;with this .prm (I didn't check) but, more&amp;nbsp;probably, there was an&amp;nbsp;mistake in prm version I've received.&lt;/DIV&gt;&lt;DIV&gt;Thanks for your answer.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Luis&lt;/DIV&gt;&lt;DIV&gt;I&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 23 Nov 2006 17:09:52 GMT</pubDate>
    <dc:creator>LuisIT</dc:creator>
    <dc:date>2006-11-23T17:09:52Z</dc:date>
    <item>
      <title>FSICE for HC08 and interrupt vectors for True-Time Simulator</title>
      <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134438#M1580</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hello all,&lt;/DIV&gt;&lt;DIV&gt;I spent&amp;nbsp;many hours before to understand that CW didn't set correctly the table interrupts in memory so True-Time Simulator wasn't able to handle, for instance,&amp;nbsp;timers interrupt and so on.&lt;/DIV&gt;&lt;DIV&gt;I put in prm file&amp;nbsp;some statements like&amp;nbsp;this :&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;VECTOR ADDRESS 0xFFEC Tim2Intp&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;and now it works ok but please could someone to help me to where I can find information about this issue ?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thank you.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Luigi&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Oct 2006 04:16:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134438#M1580</guid>
      <dc:creator>LuisIT</dc:creator>
      <dc:date>2006-10-27T04:16:02Z</dc:date>
    </item>
    <item>
      <title>Re: FSICE for HC08 and interrupt vectors for True-Time Simulator</title>
      <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134439#M1581</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hello&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Can you please be more specific?&lt;/DIV&gt;&lt;DIV&gt;Which CPU are you Targeting?&lt;/DIV&gt;&lt;DIV&gt;How did you attempt to initialize the vector table?&lt;/DIV&gt;&lt;DIV&gt;Where did you expect to see the address of the function?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;CrasyCat&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Oct 2006 15:05:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134439#M1581</guid>
      <dc:creator>CrasyCat</dc:creator>
      <dc:date>2006-10-27T15:05:26Z</dc:date>
    </item>
    <item>
      <title>Re: FSICE for HC08 and interrupt vectors for True-Time Simulator</title>
      <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134440#M1582</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Hello, sorry for big delay&amp;nbsp;with my&amp;nbsp;answer ...&lt;/DIV&gt;&lt;DIV&gt;I'm targeting GZ32 mc using FSICE (btw, the file .mem for 32K emulation chip [MCUID 043B], wasn't available in prog\mem directory, I had to create, instead 16K and 48K .mem files&amp;nbsp;&amp;nbsp;are available, why ... ?).&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;The problem is in the prm file, below pieces of sorces :&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;U&gt;FROM CODE:&lt;/U&gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;U&gt;&lt;/U&gt;&lt;/STRONG&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;#define vjmp&amp;nbsp; 0xcc&amp;nbsp;// JUMP opcode&lt;/DIV&gt;&lt;DIV&gt;typedef struct&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;char opcode;&lt;BR /&gt;&amp;nbsp;void (* const _vectab)();&lt;BR /&gt;} tIntJmpTable;&lt;/DIV&gt;&lt;DIV&gt;#pragma CONST_SEG APPLVECT&lt;BR /&gt;const tIntJmpTable ApplIntJmpTable[22] =&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* msCAN Transmit */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, CanRxIntpt,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* msCAN Receive */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, CanErrorIntpt,&amp;nbsp;&amp;nbsp;&amp;nbsp;/* msCAN Error */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, CanWakeUpIntpt,&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* msCAN Wakeup */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Timbase */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, AdcIntp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* ADC */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, KeyIntp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;/* Keyboard */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp; &amp;nbsp;/* SCI Transmit */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* SCI Receive */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* SCI Error */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* SPI Transmit */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* SPI Receive */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp;&amp;nbsp;/* TIM2 Overflow */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, Tim2CH1Intp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* TIM2 CH1 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, Tim2CH0Intp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* TIM2 CH0 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, Tim1OverIntp,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* TIM1 Overflow */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* TIM1 CH1 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp;&amp;nbsp;/* TIM1 CH0 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand,&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* PLL */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, NullHand, &amp;nbsp;&amp;nbsp;&amp;nbsp;/* IRQ1 vector handler */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, ResetIntpt,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;vjmp, ResetIntpt,&lt;BR /&gt;};&lt;BR /&gt;#pragma CONST_SEG DEFAULT&lt;/DIV&gt;&lt;DIV&gt;----------------------------------------------------------------------&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;U&gt;PRM FILE:&lt;/U&gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;U&gt;&lt;/U&gt;&lt;/STRONG&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;NAMES END&lt;/DIV&gt;&lt;DIV&gt;SECTIONS&lt;BR /&gt;...&lt;BR /&gt;&amp;nbsp;AVECT &amp;nbsp;&amp;nbsp;= READ_ONLY &amp;nbsp;&lt;STRONG&gt;0xE800 TO 0xE87F&lt;/STRONG&gt;;&lt;BR /&gt;...&lt;BR /&gt;END&lt;/DIV&gt;&lt;DIV&gt;PLACEMENT&amp;nbsp;&amp;nbsp;&lt;BR /&gt;...&lt;BR /&gt;&amp;nbsp;APPLVECT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; INTO&amp;nbsp; AVECT;&lt;BR /&gt;...&lt;BR /&gt;END&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;At the beginning I didn't check prm file but it's clear that AVECT section didn't point to correct area where interrupts source&amp;nbsp;are&amp;nbsp;located (FFD4-FFFF), indeed at address 0xE82A there is Tim2CH0Intp vector address (instead to FFF0) ...&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;It doesn't seem to me that interrupt vectors can be relocated so I'm not able to understand how it's possible that mc could run well&amp;nbsp;with this .prm (I didn't check) but, more&amp;nbsp;probably, there was an&amp;nbsp;mistake in prm version I've received.&lt;/DIV&gt;&lt;DIV&gt;Thanks for your answer.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Luis&lt;/DIV&gt;&lt;DIV&gt;I&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Nov 2006 17:09:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134440#M1582</guid>
      <dc:creator>LuisIT</dc:creator>
      <dc:date>2006-11-23T17:09:52Z</dc:date>
    </item>
    <item>
      <title>Re: FSICE for HC08 and interrupt vectors for True-Time Simulator</title>
      <link>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134441#M1583</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Hello&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;From what I can see you are not initializing the vector table 0xFFD4-0xFFFF.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;How should the linker know what you want to do with the interrupts?&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Please initialize the vector table entry to point to your interrupt jump table.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;You can use the linker command VECTOR and specify an offset there&amp;nbsp;&lt;/FONT&gt; &lt;P align="left"&gt;&lt;FONT size="2"&gt;VECTOR ADDRESS 0xFFD4 tIntJmpTable OFFSET 0x00&lt;BR /&gt;&lt;/FONT&gt;&lt;FONT size="2"&gt;VECTOR ADDRESS 0xFFD6 tIntJmpTable OFFSET 0x03&lt;BR /&gt;VECTOR ADDRESS 0xFFD8 tIntJmpTable OFFSET 0x06&lt;/FONT&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;DIV&gt;and so on.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;CrasyCat&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Nov 2006 18:49:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/CodeWarrior-for-MCU/FSICE-for-HC08-and-interrupt-vectors-for-True-Time-Simulator/m-p/134441#M1583</guid>
      <dc:creator>CrasyCat</dc:creator>
      <dc:date>2006-11-23T18:49:16Z</dc:date>
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