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Fixup overflow error in _vect...

嘉星邓 — Thu, 10 May 2018 13:02:25 GMT

Hi All,

When I upgraded from mc9s08dz60 to mc9s08dz96, I got this error:

Fixup overflow in _vect2, to SysTimer_Interrupt type 1, at offset 0xC
Fixup overflow in _vect2, to RFIRQ_Interrupt type 1, at offset 0x12
Fixup overflow in _vect2, to Cpu_Interrupt type 1, at offset 0xE
Fixup overflow in _vect2, to Cpu_Interrupt type 1, at offset 0xA

......

My code was working with mc9s12dz60, how can I fix this?

Thanks!

prm file:

Interrupt vector table:

Re: Fixup overflow error in _vect...

ZhangJennie — Fri, 11 May 2018 02:28:58 GMT

Hi Jiaxing Deng,

I wonder you have overlap vector table definition in your code.

Please upload your demo project here. I will check.

Have a great day,
Jennie Zhang

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Re: Fixup overflow error in _vect...

stanish — Fri, 11 May 2018 22:14:39 GMT

Hi,

Please check where are the ISRs placed into. I assume they are placed in paged/banked memory - DEFAULT_ROM.

I'd recommend you to add an explicit pragma to place the ISR into non-banked memory segment e.g see the snippet below:

#pragma push
#pragma CODE_SEG __NEAR_SEG NON_BANKED
interrupt void SysTimer_Interrupt(void);
#pragma pop‍‍‍‍‍‍‍‍

Hope it helps.

Re: Fixup overflow error in _vect...

嘉星邓 — Sat, 12 May 2018 05:32:23 GMT

Hi Jennie Zhang,

Thanks for your reply.

I'm sorry I can't upload my project, but I solved the problem through @Stanislav Sliva's tips.

Thank you again.

Re: Fixup overflow error in _vect...

嘉星邓 — Sat, 12 May 2018 05:49:05 GMT

Hi Stanislav,

Thanks for your reply, I according to your suggestions tried and solved the problem.

But I don't understand why can't the ISRs are placed in paged/banked memory, My interrupt vector table are placed in a fixed cpu address @0xFFC0.

Best Regards!

Jiaxing Deng

Re: Fixup overflow error in _vect...

stanish — Fri, 18 May 2018 13:58:46 GMT

This is because of how interrupt vector table is implemented on HCS08/HCs12 architectures.

There are just 16 bits (near) pointer dedicated to each interrupt vector - this is hardwired.

It makes sense since for a long time HC08 cores didn't have more than 64kB of flash memory. To keep backward compatibility it is the same on devices with more 64kB of Flash.

Now on such a devices you need to take special care about where ISR routines are placed so they can be accessed by near 16bit pointer.

Hope it helps.

Stan