topic Re: QCVS DDR margin tool in CodeWarrior Development Tools

QCVS DDR margin tool

OneNote — Wed, 15 Jun 2022 06:06:04 GMT

In our latest codewarriro QCVS, the margin page of DDR validation doesn't have Margin stage as scenarios, only has Diags margin stage. Why this happen? What's the cause?

Thanks.

Re: QCVS DDR margin tool

OneNote — Wed, 15 Jun 2022 06:08:38 GMT

Re: QCVS DDR margin tool

yipingwang — Fri, 17 Jun 2022 03:50:00 GMT

What processor are you using now?

Which version QCVS tool are you using?

Re: QCVS DDR margin tool

OneNote-0 — Fri, 17 Jun 2022 03:52:40 GMT

Thanks, Yiping.

Processor: LX2160A

QCVS version: 4.23

Re: QCVS DDR margin tool

yipingwang — Fri, 17 Jun 2022 04:27:27 GMT

Margin stage is removed since QCVS 4.23 2020.11 release.

Margin stage scenario is no longer available for LX2, but is should be available for the rest of devices.

If further information is needed, please feel free to let me know.

Re: QCVS DDR margin tool

OneNote-0 — Fri, 17 Jun 2022 04:40:59 GMT

Thanks.

Further question: how to test margin? use diag margin stage?

Re: QCVS DDR margin tool

yipingwang — Fri, 17 Jun 2022 06:09:24 GMT

I just got confirmation from the development team.

Yes, you should use the diag margin stage.

Re: QCVS DDR margin tool

OneNote — Fri, 17 Jun 2022 09:46:17 GMT

Thanks.

Now it's back to 4.22.

There is a new issue happen when run the margin test.

Log attached.

Re: QCVS DDR margin tool

yipingwang — Fri, 17 Jun 2022 09:56:05 GMT

Please open CCS console on the right bottom of your task bar, type "log v", then connect to the target board again, the low level CCS log will be printed out.

Please send the CCS console log to me to do more investigation.

Re: QCVS DDR margin tool

OneNote — Fri, 17 Jun 2022 10:30:46 GMT

Is this what you want? Thanks.

Re: QCVS DDR margin tool

OneNote — Fri, 17 Jun 2022 11:42:25 GMT

Re: QCVS DDR margin tool

yipingwang — Mon, 20 Jun 2022 02:52:58 GMT

It failed at "reset_to_debug". If the RCW is valid, probably there is hardware design problem of the JTAG interface on your custom board.

Re: QCVS DDR margin tool

yipingwang — Mon, 20 Jun 2022 03:00:57 GMT

Is it possible to provide your JTAG design schematics for the custom board?

Re: QCVS DDR margin tool

OneNote — Tue, 21 Jun 2022 06:35:45 GMT

I will provide it in case submitted. Thanks.

Re: QCVS DDR margin tool

OneNote — Tue, 21 Jun 2022 05:55:55 GMT

Measured the reset signals, when nRESET is low, PORESET_B also is low. And also found the HRESET_B is low and keep low always.Is it a clue?

Re: QCVS DDR margin tool

yipingwang — Tue, 21 Jun 2022 09:59:30 GMT

Would you please refer to "3.2 Working with bareboard application" in the attached document to create a board board project and run it on your target board.

Please click "Target Connections->LX2160A_RDB(1)->Edit->Target Initialization File",

please modify "USE_SAFE_RCW = False" to "USE_SAFE_RCW = True".

Then connect to the target board, and send CCS console log to me, I just want to check whether the core can be stopped.

Re: QCVS DDR margin tool

yipingwang — Tue, 21 Jun 2022 10:26:50 GMT

Please also try the following commands in CCS console.

delete all

config cc cwtap:<ip>

ccs::config_chain {lx2160a dap}

display ::ccs::get_config_chain

::ccs::stop_multi_core {21}

::ccs::reset_to_debug

Re: QCVS DDR margin tool

OneNote — Tue, 21 Jun 2022 11:01:07 GMT

Re: QCVS DDR margin tool

yipingwang — Tue, 21 Jun 2022 11:13:19 GMT

Please try to run a bareboard application with hard-coded RCW as I mentioned in my previous post.

Re: QCVS DDR margin tool

OneNote — Tue, 21 Jun 2022 11:14:11 GMT