DUART speed is wrong for non-default T208x QDS SYSCLK

chuckcorley — Thu, 08 Dec 2016 16:42:29 GMT

The "Welcome to CodeWarrior" out-of-the-box project runs successfully for the default SYSCLK setting on the board (66MHz - SW3[1:4] = 0) but if you change SW4 to another SYSCLK speed the project will output garbage to the terminal.

The problem appears to be with the DUART library. If you build your own archive library for the DUART, you can make the following changes in duart_config.c and fix it.

// unsigned char CLK_SPD_Reg = (*(unsigned char *)(QIXIS_BASE + CLK_SPD_OFFSET));

unsigned char CLK_SPD_Reg = (*(unsigned char *)(QIXIS_BASE + CLK_SPD1_OFFSET));

switch ( CLK_SPD_Reg & 0x07 )

{

case 0x0: systemClock = 67; break;

// case 0x1: systemClock = 100; break;

case 0x1: systemClock = 83; break;

// case 0x2: systemClock = 125; break;

case 0x2: systemClock = 100; break;

// case 0x3: systemClock = 133; break;

case 0x3: systemClock = 125; break;

// case 0x4: systemClock = 75; break;

case 0x4: systemClock = 133; break;

// case 0x5: systemClock = 83; break;

case 0x5: systemClock = 150; break;

case 0x6: systemClock = 160; break;

case 0x7: systemClock = 167; break;

default : systemClock = 100; break;

}

Where CLK_SPD1_OFFSET is added to the definitions in duart_config.h as

#define CLK_SPD1_OFFSET 0x30

The root cause of this problem is the fact that the QIXIS fpga register being polled for SYSCLK (and DDRCLK) on the T2081 QDS has been moved from CLK_SPD_OFFSET 0x07 to CLK_SPD1_OFFSET 0x30. The old register has been deprecated and the encoding of the speeds has changed as shown above. This is documented in the QorIQ T1040 Development System Manual. The T1040 QDS is the basis of the T2081 QDS.I believe this same change affects other QDS systems as well, like the T2080. All one would have to do is to compare the duart_config.c file at {CodeWarriorInstallationDirectory}\PA\PA_Support\Serial\[platform of interest] to the QIXIS programming section in the platform reference manual.

BTW, I find the directions in the README for building a custom DUART archive file to be out-of-date. It says:

... to rebuild the UART library:

1. From your CW install directory, import the

<CWInstallDir>\PA\PA_Support\Serial\T2081QDS_aeabi_32bit_serial (or T2081QDS_aeabi_64bit_serial) project

2. Switch to the correspondent Build Target (eg DUARTA_UC_32bit).

Open duart_config.h file and change the value of the "MMR_BASE" accordingly

3. Re-build the project (and copy the output library in you project)

I can't find that project but was able to create a new archive file project, copy in the contents of {CodeWarriorInstallationDirectory}\PA\PA_Support\Serial\Common and {CodeWarriorInstallationDirectory}\PA\PA_Support\Serial\T1040QDS_aeabi_32bit_serial\Source\* . Edit the two files above found in the latter directory as shown above and build an archive file to replace the default UART1_*.a file.

Re: DUART speed is wrong for non-default T208x QDS SYSCLK

yipingwang — Tue, 13 Dec 2016 09:45:28 GMT

The user could import the attached projects in CodeWarrior and modify the configuration in the header file.

Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

topic Re: DUART speed is wrong for non-default T208x QDS SYSCLK in CodeWarrior Development Tools

DUART speed is wrong for non-default T208x QDS SYSCLK

Re: DUART speed is wrong for non-default T208x QDS SYSCLK