ADLSTAT REGISTER / High Limit Interrupt Help Please!

Myles — Mon, 27 Jun 2011 23:02:19 GMT

Hi I have a MC56F83XX board and upon reading the manual I come up with this paragraph.

&quote;2.12.7 ADC Limit Status Register (ADLSTAT)

The Limit Status register latches in the result of the comparison between the result of the sample

and the respective limit register, ADHLMT0-7 and ADLLMT0-7. For an example, if the result

for the channel programmed in SAMPLE0 is greater than the value programmed into the High

Limit register zero, then the HLS0 bit is set to one. An interrupt is generated if the HLMTIE bit is

set in ADCR1. A bit may only be cleared by writing 1 to that specific bit. These bits are sticky.

Once set, the bits require a specific modification to clear them. They are not cleared

automatically by subsequent conversions."

I am not sure I understand this correctly. If I am trying to see if a bit that has triggered the high limit interrupt would this be the correct code? Obviously this code is just an example and the if logic is not conclusive. I have tried to look up other peoples code but haven't found any, the only thing I have found is Init code and I have seen people setting the ADLSTAT to FFFF, which seems to be the opposite of what I am doing. Any input is greatly appreciated. Thanks!

int Values[8]; AD1_GetValue((int *) Values); LimitStatusTmp = getReg(ADCA_ADLSTAT);

int Curr_High_A

int bit; //flag variable to set high bit number if (LimitStatusTmp & 0x0100) { bit = 8; } Curr_High_A = Values[bit-8]; clrRegBits(ADCA_ADCR1,0x0080);

Re: ADLSTAT REGISTER / High Limit Interrupt Help Please!

admin — Tue, 12 Jul 2011 20:34:40 GMT

Zero Crossing, Low Limit, and High Limit Interrupt share one interrupt vector - ADC_ERR_INT. So if you enable this interrupts via ADCTL1 register (setting 1 in ZCIE, LLMTIE, HLMTIE bits) only one interrupt will occur. Interrupts will be generated if any HLSx, LLSx, ZCSx bits set (ADLSTAT, ADZCSTAT registers) and ADC_ERR_INT-interrupt enabled.
But to clear HLSx, LLSx, ZCSx bits you need to write 1 in this bits. So your interrupt handlier should be like this

#pragma interrupt alignsp saveallvoid ADC1_InterruptERR(void){  register word LimitStatusTmp;  register word ZeroStatusTmp;  word timeR, time;  int val;    LimitStatusTmp = getReg(ADCA_ADLSTAT);  ZeroStatusTmp = getReg(ADCA_ADZCSTAT);  setReg(ADCA_ADLSTAT,65535);          /* Clear limit status flags */  setReg(ADCA_ADZCSTAT,255);           /* Clear Zero crossing status flags */// another actions}

If you want to disable High Limit, Low Limit and Zero Crossing interrupts you need to use

clrRegBits(ADCA_ADCR1,0x0100); // for high limitclrRegBits(ADCA_ADCR1,0x0200); // for low limitclrRegBits(ADCA_ADCR1,0x0400); // for zero crossing

But if you disable them - interrupt does not generate next time.

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ADLSTAT REGISTER / High Limit Interrupt Help Please!

Re: ADLSTAT REGISTER / High Limit Interrupt Help Please!