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    <title>topic Re: CodeWarrior masking additional interrupts on 56F803 in Classic/Legacy CodeWarrior</title>
    <link>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175698#M3757</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hello&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Attached to this post you will find an example.&lt;/DIV&gt;&lt;DIV&gt;This example has 3 c source files and other files like ISR table, startup, library, etc ...&lt;/DIV&gt;&lt;DIV&gt;Please have a look to the isr.c file.&lt;/DIV&gt;&lt;DIV&gt;This file has the initIsr function. This function is called by the main function on the beginning of the application.&lt;/DIV&gt;&lt;DIV&gt;Extract of the Code:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;void initIsr ()&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;asm (bfset #$0100,sr);&lt;BR /&gt;&amp;nbsp;asm (bfclr #$0200,sr);&amp;nbsp;&amp;nbsp;&amp;nbsp;/* allow lowest priority */&lt;BR /&gt;&amp;nbsp;asm (bfset #$fe12,X:IPR);&amp;nbsp;&amp;nbsp;/* enable both IRQ A &amp;amp; B, and all other interrupts */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;asm (bfset #$0100,X:GPR10);&amp;nbsp;&amp;nbsp;/* Timer A Ch 0 lowest priority */&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Pascal&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 02 Jan 2008 21:30:19 GMT</pubDate>
    <dc:creator>trytohelp</dc:creator>
    <dc:date>2008-01-02T21:30:19Z</dc:date>
    <item>
      <title>CodeWarrior masking additional interrupts on 56F803</title>
      <link>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175697#M3756</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I had a surprising (to me) problem with CodeWarrior on the 56F803. While running a slow, low-priority interrupt routine, CW masks all other peripheral interrupts by setting I1 in the status register high. This delays my SPI0 read interrupt sufficiently that I lose incoming serial data. I tried it with version 7.3 and 8.1.1a.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The slow interrupt handler uses #pragma interrupt saveall; the fast ones use #pragma interrupt.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I "fixed" it by putting asm(BFCLR #$0200,SR); at the start of the low-priority interrupt handler, but this seems like a bit of a hack, and I am concerned that there may be more involved.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Why did CW mask the interrupts, and what possible problems am I creating by un-masking them? Is there a compiler setting to change this behaviour?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks!&lt;/SPAN&gt;&lt;BR /&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 01 Jan 2008 07:34:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175697#M3756</guid>
      <dc:creator>dynode</dc:creator>
      <dc:date>2008-01-01T07:34:28Z</dc:date>
    </item>
    <item>
      <title>Re: CodeWarrior masking additional interrupts on 56F803</title>
      <link>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175698#M3757</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hello&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Attached to this post you will find an example.&lt;/DIV&gt;&lt;DIV&gt;This example has 3 c source files and other files like ISR table, startup, library, etc ...&lt;/DIV&gt;&lt;DIV&gt;Please have a look to the isr.c file.&lt;/DIV&gt;&lt;DIV&gt;This file has the initIsr function. This function is called by the main function on the beginning of the application.&lt;/DIV&gt;&lt;DIV&gt;Extract of the Code:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;void initIsr ()&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;asm (bfset #$0100,sr);&lt;BR /&gt;&amp;nbsp;asm (bfclr #$0200,sr);&amp;nbsp;&amp;nbsp;&amp;nbsp;/* allow lowest priority */&lt;BR /&gt;&amp;nbsp;asm (bfset #$fe12,X:IPR);&amp;nbsp;&amp;nbsp;/* enable both IRQ A &amp;amp; B, and all other interrupts */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;asm (bfset #$0100,X:GPR10);&amp;nbsp;&amp;nbsp;/* Timer A Ch 0 lowest priority */&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Pascal&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Jan 2008 21:30:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175698#M3757</guid>
      <dc:creator>trytohelp</dc:creator>
      <dc:date>2008-01-02T21:30:19Z</dc:date>
    </item>
    <item>
      <title>Re: CodeWarrior masking additional interrupts on 56F803</title>
      <link>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175699#M3758</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Pascal,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thank you for the example, it will be useful in the future. But unless I missed something, I don't think it addresses my immediate question.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;The example uses Timer A0 at the lowest priority level. I am using Timer C0 for something similar, also at the lowest interrupt priority; it interrupts and runs sensor and control code once per millisecond. Its handler uses #pragma saveall.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I also have several other interrupt handlers running, including CAN, SPI, and SCI. The problem appeared when I tried to receive serial data from SCI0 into a buffer at 115.2 Kbaud. The interrupt handler for this is only about&amp;nbsp;10 lines of C code, and it uses #pragma interrupt. I gave this interrupt handler the highest priority level, because this MCU has only a one-byte hardware receive buffer. Arriving data must be moved to the software buffer within about 80 microseconds. The software buffer is a global array, which of course is also accessed by the parsing function which runs during the TMRC0 interrupt handler.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;The interrupt enable bits in the Status Register (SR) are initially set to allow interrupts, during the DSP56F803_init.c function. However, at some point bit I1 is turned on, disabling peripheral interrupts. I think it happens during the TMRC0 handler, and it must be that&amp;nbsp;I1 is turned off again later, because all of the higher level interrupts do run eventually. It just happens to be too late for SCI0 at 115.2 Kbaud.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;If I set I1 to zero with asm(bfclr #$0200,SR); at the start of the TMRC0 handler, all seems well, and no incoming serial data is lost. This is not the case if I add a bfclr line to my startup and initialization code, not surprisingly.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Although&amp;nbsp;the fix&amp;nbsp;described above seems to&amp;nbsp;work, it seemed to me that this interrupt masking was done by the compiler for some specific reason, or perhaps as a result of some specific setting, and I wondered what it was. I would like to have some confidence that my interrupts are running on time, even when the resulting problems are not as obvious. I have not&amp;nbsp;been able to find&amp;nbsp;any reference to this in the documentation yet.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thanks!&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Jan 2008 04:06:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175699#M3758</guid>
      <dc:creator>dynode</dc:creator>
      <dc:date>2008-01-03T04:06:39Z</dc:date>
    </item>
    <item>
      <title>Re: CodeWarrior masking additional interrupts on 56F803</title>
      <link>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175700#M3759</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thanks for the details.&lt;/DIV&gt;&lt;DIV&gt;Do you use an example delivered on the installation ?&lt;/DIV&gt;&lt;DIV&gt;Do yo use Processor Expert ?&lt;/DIV&gt;&lt;DIV&gt;Is it possible to have the example and point me exactly where is the problem in th code ?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Pascal&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Jan 2008 16:17:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Classic-Legacy-CodeWarrior/CodeWarrior-masking-additional-interrupts-on-56F803/m-p/175700#M3759</guid>
      <dc:creator>trytohelp</dc:creator>
      <dc:date>2008-01-03T16:17:04Z</dc:date>
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