topic ColdFire IRQ level control in ColdFire/68K Microcontrollers and Processors

ColdFire IRQ level control

PA_Dan — Thu, 06 Apr 2006 02:37:57 GMT

Can someone please confirm the following statement copied from one of the other threads?

"When you are in an interrupt routine you don't want to be interrupted by a
interrupt with a lower priority. That is when your in a level 3 routine you
really aren't interested in level 2 routines.

The 68k took care of this automatically, the Coldfire does not, however the
Coldfire guarentees the first instruction in an interrupt routine is
executed. You take advantage of this and solve the problem by putting an
instruction that writes to the status register that either raises the level
or locks out interrupts depending on how you feel it should be done. "

Dan

Re: ColdFire IRQ level control

mnorman — Thu, 06 Apr 2006 22:50:07 GMT

That statement is incorrect. ColdFire behaves the same way that the 68K did in this regard.

Before executing an exception/interrupt handler, the ColdFire core will store the exception stack frame (including the SR) and set the SR[I] mask field to the level of the interrupt being acknowledged. This masks interrupts at the current level or below (except for the non-maskable level 7).

Unlike the 68K however, the ColdFire core will not sample for interrupts again until after the first instruction of the interrupt/exception routine has been executed. This allows the software to raise the interrupt level even further if needed.

Re: ColdFire IRQ level control

PA_Dan — Thu, 06 Apr 2006 22:54:42 GMT

Whew! Thanks.