<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Inc size for BCHG #6, (A2)+ in ColdFire/68K Microcontrollers and Processors</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Inc-size-for-BCHG-6-A2/m-p/198362#M8962</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Kef. Got it.&amp;nbsp; An inc by 1 makes sense if mem[a2] just represents an 8-bit value.&amp;nbsp; However, I would think the more common case on a 32-bit cpu would be to inc by 4 because mem[a2] is the ls byte of a 32-bit value.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Tim&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 13 Jul 2009 21:21:48 GMT</pubDate>
    <dc:creator>tupdegrove</dc:creator>
    <dc:date>2009-07-13T21:21:48Z</dc:date>
    <item>
      <title>Inc size for BCHG #6, (A2)+</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Inc-size-for-BCHG-6-A2/m-p/198360#M8960</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Test M[a2].[6]&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I know this is a byte operation but is register a2 post incremented by 1 or 4 bytes?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Tim&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 12 Jul 2009 01:56:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Inc-size-for-BCHG-6-A2/m-p/198360#M8960</guid>
      <dc:creator>tupdegrove</dc:creator>
      <dc:date>2009-07-12T01:56:17Z</dc:date>
    </item>
    <item>
      <title>Re: Inc size for BCHG #6, (A2)+</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Inc-size-for-BCHG-6-A2/m-p/198361#M8961</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;What's this: Test M[a2].[6] ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;All (Ax)+ like operations will increment Ax by sizeof of operand. Sizeof is&amp;nbsp;1&amp;nbsp;in your case (BCHG.B), and A2 will be incremented by 1.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 12 Jul 2009 14:33:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Inc-size-for-BCHG-6-A2/m-p/198361#M8961</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2009-07-12T14:33:57Z</dc:date>
    </item>
    <item>
      <title>Re: Inc size for BCHG #6, (A2)+</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Inc-size-for-BCHG-6-A2/m-p/198362#M8962</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Kef. Got it.&amp;nbsp; An inc by 1 makes sense if mem[a2] just represents an 8-bit value.&amp;nbsp; However, I would think the more common case on a 32-bit cpu would be to inc by 4 because mem[a2] is the ls byte of a 32-bit value.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Tim&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Jul 2009 21:21:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Inc-size-for-BCHG-6-A2/m-p/198362#M8962</guid>
      <dc:creator>tupdegrove</dc:creator>
      <dc:date>2009-07-13T21:21:48Z</dc:date>
    </item>
  </channel>
</rss>

