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    <title>ColdFire/68K Microcontrollers and ProcessorsのトピックRe: 5282 problem with QSPI CLK</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131330#M893</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;YOU must set&amp;nbsp; your pin in input or in output as this register:&lt;BR /&gt;&lt;BR /&gt;&lt;I&gt;MCF_GPIO_DDRQS = (0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; | MCF_GPIO_DDRQS_DDRQS0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; | MCF_GPIO_DDRQS_DDRQS3&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; | MCF_GPIO_DDRQS_DDRQS2);&lt;BR /&gt;&lt;BR /&gt;I have a coldfire 52233 but i think that your register is the same.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/I&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 04 Jun 2007 21:26:50 GMT</pubDate>
    <dc:creator>GUNNM</dc:creator>
    <dc:date>2007-06-04T21:26:50Z</dc:date>
    <item>
      <title>5282 problem with QSPI CLK</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131327#M890</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi all,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I use the QSPI of the MCF5282 and I've a problem to generate the clock.&lt;/DIV&gt;&lt;DIV&gt;I'm need to communicate with 4 CAN, and they need a low state for start a convertion on the Chip select&lt;/DIV&gt;&lt;DIV&gt;I was inspired of a source code of different solution on your forum.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thanks for your help in advance.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;HR /&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;/* Enable QSPI Pins Primary Functions */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;&amp;nbsp;MCF5282_GPIO_PQSPAR = 0x7F;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;/* set up delay from chip select to first edge of QSPI clock */&amp;nbsp;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QMR=0xB302;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDLYR=0x0000;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QIR=0xD00F;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QIR |= MCF5282_QSPI_QIR_SPIF;&amp;nbsp; /* Make sure SPIF is cleared */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;/* set queue pointer to the first command RAM entry */ &amp;nbsp;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QAR=0x0020;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;/* command entry for transfer to QSPI_CS0 */&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0x7E00;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0x7E00;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0x7D00;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0x7D00;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0x7B00;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0x7B00;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0x7700;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0x7700;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;/* set queue pointer to the first data RAM entry */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;MCF5282_QSPI_QAR = 0x0000;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;/* data RAM entry for transfer to QSPI_CS0 */&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0xFFF;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0xFFF;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0xFFF;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0xFFF;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0xFFF;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0xFFF;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0xFFF;&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDR=0xFFF;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;/* set up wrap register for 8 12-bit transfers */&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QWR=0x0F00;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;/*start the transfer */&lt;BR /&gt;&amp;nbsp;MCF5282_QSPI_QDLYR |= MCF5282_QSPI_QDLYR_SPE;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;while(!(MCF5282_QSPI_QIR &amp;amp; MCF5282_QSPI_QIR_SPIF)){}&amp;nbsp;// Wait till transfers are complete&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="font-size: 2;"&gt;MCF5282_QSPI_QAR=0x0010;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //Receive RAM selected&lt;BR /&gt;DATA = MCF5282_QSPI_QDR;&lt;/SPAN&gt;&amp;nbsp;&lt;HR /&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Apr 2007 14:38:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131327#M890</guid>
      <dc:creator>Mikeeulkeul</dc:creator>
      <dc:date>2007-04-20T14:38:53Z</dc:date>
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    <item>
      <title>Re: 5282 problem with QSPI CLK</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131328#M891</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hi, In QWR register, set bit CSIV to 1 if you need chip select as active low; also set correctly the length of the queue: you want 8 transfers and set instead ENDQP to 'F' (16 transfers). Regards, yoan&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Apr 2007 17:24:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131328#M891</guid>
      <dc:creator>Pai</dc:creator>
      <dc:date>2007-04-20T17:24:53Z</dc:date>
    </item>
    <item>
      <title>Re: 5282 problem with QSPI CLK</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131329#M892</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Ok, thanks yoan.&lt;/DIV&gt;&lt;DIV&gt;But then I look my QSPI_CLK output, I don't see the QSPI Clock.&lt;/DIV&gt;&lt;DIV&gt;I don't know if my clock is correctly generated, but I see the QSPI_CLK&amp;nbsp;with an oscilloscope I've a constant signal.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Regards.&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Apr 2007 18:50:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131329#M892</guid>
      <dc:creator>Mikeeulkeul</dc:creator>
      <dc:date>2007-04-20T18:50:04Z</dc:date>
    </item>
    <item>
      <title>Re: 5282 problem with QSPI CLK</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131330#M893</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;YOU must set&amp;nbsp; your pin in input or in output as this register:&lt;BR /&gt;&lt;BR /&gt;&lt;I&gt;MCF_GPIO_DDRQS = (0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; | MCF_GPIO_DDRQS_DDRQS0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; | MCF_GPIO_DDRQS_DDRQS3&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; | MCF_GPIO_DDRQS_DDRQS2);&lt;BR /&gt;&lt;BR /&gt;I have a coldfire 52233 but i think that your register is the same.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/I&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Jun 2007 21:26:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5282-problem-with-QSPI-CLK/m-p/131330#M893</guid>
      <dc:creator>GUNNM</dc:creator>
      <dc:date>2007-06-04T21:26:50Z</dc:date>
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