<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic M52259DEMO - DMA transfers to peripherals in ColdFire/68K Microcontrollers and Processors</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195496#M8646</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I've been playing with DMA transfers and I can quite happly move data from memory to memory. My problem is moving data from memory to peripherals.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm using Processor Expert Init_DMA to set everything up and if specify the source as (uint8)&amp;amp;MemorySource and the destination as (uint8)&amp;amp;MemoryDestination, with a 1 byte transfer then this works fine.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If however, I change the destination to (uint8)&amp;amp;PWMDTY2 for example (I've tried others) then the transfer fails with a BED error in DSR2 -&amp;gt; "The DMA channel terminated with a bus error during the write portion of a transfer."&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Now in the 52259 Ref Manual, 22.4.3.2 gives " If the transfer is from memory to a peripheral device, DARn is loaded with the address of the peripheral data register. This address can be any aligned byte address."&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Unfortunately, I'm not sure what it means by aligned byte address. Can anyone enlighten me?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance - Colin&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 26 Apr 2010 01:25:34 GMT</pubDate>
    <dc:creator>BatTech</dc:creator>
    <dc:date>2010-04-26T01:25:34Z</dc:date>
    <item>
      <title>M52259DEMO - DMA transfers to peripherals</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195496#M8646</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I've been playing with DMA transfers and I can quite happly move data from memory to memory. My problem is moving data from memory to peripherals.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm using Processor Expert Init_DMA to set everything up and if specify the source as (uint8)&amp;amp;MemorySource and the destination as (uint8)&amp;amp;MemoryDestination, with a 1 byte transfer then this works fine.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If however, I change the destination to (uint8)&amp;amp;PWMDTY2 for example (I've tried others) then the transfer fails with a BED error in DSR2 -&amp;gt; "The DMA channel terminated with a bus error during the write portion of a transfer."&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Now in the 52259 Ref Manual, 22.4.3.2 gives " If the transfer is from memory to a peripheral device, DARn is loaded with the address of the peripheral data register. This address can be any aligned byte address."&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Unfortunately, I'm not sure what it means by aligned byte address. Can anyone enlighten me?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance - Colin&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 26 Apr 2010 01:25:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195496#M8646</guid>
      <dc:creator>BatTech</dc:creator>
      <dc:date>2010-04-26T01:25:34Z</dc:date>
    </item>
    <item>
      <title>Re: M52259DEMO - DMA transfers to peripherals</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195497#M8647</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Colin&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;"aligned byte address" doesn't make a lot of sense since a byte is always aligned.&lt;/P&gt;&lt;P&gt;I checked in some existing projects and found one reading from an edge port via DMA (EPPDR0 is at the address (IPSBAR + 0x130005)) so this does suggest that there should be no problems reading from an odd address.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The DMA controller doesn't however automatically have full rights to access parts of memory, therefore you may be seeing access violations due to this. Make sure that you have given the controller adequate rights by doing:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;GPACR0 = SUP_USER_FULL_ACCESS;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // enable peripheral SRAM access (value is 0x4)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;others which may be useful are:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; PACR1 = 0x04;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; // enable DMA to access FLASH&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; GPACR1 = 0x04;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.uTasker.com" rel="nofollow" target="_self"&gt;www.uTasker.com&lt;/A&gt;&lt;BR /&gt;- OS, TCP/IP stack, USB, device drivers and simulator for M521X, M521XX, M5221X, M5222X, M5223X, M5225X. One package does them all - "&lt;EM&gt;Embedding it better...&lt;/EM&gt;"&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 26 Apr 2010 01:59:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195497#M8647</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2010-04-26T01:59:53Z</dc:date>
    </item>
    <item>
      <title>Re: M52259DEMO - DMA transfers to peripherals</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195498#M8648</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Mark you are a star. Now stop answering silly questions on a Sunday night and find yourself a beer.&lt;IMG alt=":smileywink:" class="emoticon emoticon-smileywink" id="smileywink" src="http://freescale.i.lithium.com/i/smilies/16x16_smiley-wink.gif" title="Smiley Wink" /&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;An alternative solution i've found is to set the MPR2 bit in the MPR register to elevate the DMA controllers access rights.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;(The HC08 devices were so much simpler....)&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 26 Apr 2010 04:10:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195498#M8648</guid>
      <dc:creator>BatTech</dc:creator>
      <dc:date>2010-04-26T04:10:58Z</dc:date>
    </item>
    <item>
      <title>Re: M52259DEMO - DMA transfers to peripherals</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195499#M8649</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hi Gonzalo, I'm Pablo, Have you solved your problem regarding DMA and UART?? I've exactly the same problem, on same board, and I'm still working on it without succes... Thanks in advance. Pablo.&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 05 Feb 2011 10:18:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195499#M8649</guid>
      <dc:creator>pslavkin</dc:creator>
      <dc:date>2011-02-05T10:18:40Z</dc:date>
    </item>
    <item>
      <title>Re: M52259DEMO - DMA transfers to peripherals</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195500#M8650</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please do not cross-post questions in the forums.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;---Tom&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 07 Feb 2011 21:02:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/M52259DEMO-DMA-transfers-to-peripherals/m-p/195500#M8650</guid>
      <dc:creator>J2MEJediMaster</dc:creator>
      <dc:date>2011-02-07T21:02:20Z</dc:date>
    </item>
  </channel>
</rss>

