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    <title>topic 5208, Data Cache, Ethernet buffers in ColdFire/68K Microcontrollers and Processors</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5208-Data-Cache-Ethernet-buffers/m-p/129847#M706</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm working on an ethernet application with the 5208. I store the buffer descriptors for the FEC in the internal SRAM but the ethernet buffers itself in the SDRAM. Everything works well with the data cache turned off. But i would like to use the data cache in my application.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Right now i'm working with the M5208EVB. I want to use 1 MB for buffers (not cached). How can i set this up? Is it possible to use the data cache and the fec with the ethernet buffers residing is SDRAM at the same time?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I already tried the following:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I double the size of the SDRAM (SDCS0[CSSZ] = 64 MByte instead of 32 MByte). This gives me the same memory twice. Now i set up the cache to cache only the first 32 MByte. I use the linker to take care that the buffers are accessed at an uncached address. It seems to work fine. The question here: Is it ok to do it like this? What happens with the SDRAM refesh? Is the SDRAM refreshed twice? Is there a better way to do it?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;weltreisender75&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 11 Sep 2006 16:30:37 GMT</pubDate>
    <dc:creator>weltreisender75</dc:creator>
    <dc:date>2006-09-11T16:30:37Z</dc:date>
    <item>
      <title>5208, Data Cache, Ethernet buffers</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5208-Data-Cache-Ethernet-buffers/m-p/129847#M706</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm working on an ethernet application with the 5208. I store the buffer descriptors for the FEC in the internal SRAM but the ethernet buffers itself in the SDRAM. Everything works well with the data cache turned off. But i would like to use the data cache in my application.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Right now i'm working with the M5208EVB. I want to use 1 MB for buffers (not cached). How can i set this up? Is it possible to use the data cache and the fec with the ethernet buffers residing is SDRAM at the same time?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I already tried the following:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I double the size of the SDRAM (SDCS0[CSSZ] = 64 MByte instead of 32 MByte). This gives me the same memory twice. Now i set up the cache to cache only the first 32 MByte. I use the linker to take care that the buffers are accessed at an uncached address. It seems to work fine. The question here: Is it ok to do it like this? What happens with the SDRAM refesh? Is the SDRAM refreshed twice? Is there a better way to do it?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;weltreisender75&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Sep 2006 16:30:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5208-Data-Cache-Ethernet-buffers/m-p/129847#M706</guid>
      <dc:creator>weltreisender75</dc:creator>
      <dc:date>2006-09-11T16:30:37Z</dc:date>
    </item>
    <item>
      <title>Re: 5208, Data Cache, Ethernet buffers</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5208-Data-Cache-Ethernet-buffers/m-p/129848#M707</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Your solution should work as long as both the core and FEC are addressing the buffers at their uncached addresses.&amp;nbsp;Basically you don't ever want to access the corresponding address in the cached memory space.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;The SDRAM refreshes won't be affected.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Regards,&lt;/DIV&gt;&lt;DIV&gt;Melissa&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Sep 2006 02:56:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/5208-Data-Cache-Ethernet-buffers/m-p/129848#M707</guid>
      <dc:creator>melissa_hunter</dc:creator>
      <dc:date>2006-09-14T02:56:16Z</dc:date>
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