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    <title>ColdFire/68K Microcontrollers and ProcessorsのトピックRe: MCF5485 Bootrom Vector and code segment placement</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5485-Bootrom-Vector-and-code-segment-placement/m-p/170895#M6335</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The longword at address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC (see Reset exception description in table 3-23 of the reference manual.)&amp;nbsp; This access will always occur on FBCS0 by virtue of the Global Chip-Select operation.&amp;nbsp; See section 17.1.5.2 of the reference manual for more information about Global Chip-Select operation.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 29 Jan 2010 06:21:33 GMT</pubDate>
    <dc:creator>KenJohnson</dc:creator>
    <dc:date>2010-01-29T06:21:33Z</dc:date>
    <item>
      <title>MCF5485 Bootrom Vector and code segment placement</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5485-Bootrom-Vector-and-code-segment-placement/m-p/170894#M6334</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am new to the ColdFire environment and trying to understand the placement of the initial ROM interrupt vector and code space.&amp;nbsp; I have seen some linker files that seemed to have placed the initial interrupt vector at the address 0xFFE0_0000 which is 2MB prior to the end of addressable space.&amp;nbsp; I saw another linker file that seemed to place the ROM interrupt vectore table at 0xFF80_0000, 8MB below the end of addressable space.&amp;nbsp; I have tried searching through the various reference manuals and cannot seem to fine where the CPU will fetch the initial Program Counter from index 0 of the ROM vector table. Can someone please indicate how the CPU determines the address from which it will fetch the initial PC on start-up?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Jan 2010 05:12:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5485-Bootrom-Vector-and-code-segment-placement/m-p/170894#M6334</guid>
      <dc:creator>shekel</dc:creator>
      <dc:date>2010-01-29T05:12:48Z</dc:date>
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    <item>
      <title>Re: MCF5485 Bootrom Vector and code segment placement</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5485-Bootrom-Vector-and-code-segment-placement/m-p/170895#M6335</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The longword at address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC (see Reset exception description in table 3-23 of the reference manual.)&amp;nbsp; This access will always occur on FBCS0 by virtue of the Global Chip-Select operation.&amp;nbsp; See section 17.1.5.2 of the reference manual for more information about Global Chip-Select operation.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Jan 2010 06:21:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5485-Bootrom-Vector-and-code-segment-placement/m-p/170895#M6335</guid>
      <dc:creator>KenJohnson</dc:creator>
      <dc:date>2010-01-29T06:21:33Z</dc:date>
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