topic Re: Simple Timer Interupt. in ColdFire/68K Microcontrollers and Processors

Simple Timer Interupt.

newguy — Fri, 30 Nov 2007 04:16:23 GMT

Looking to create a 100us interupt with an ISR. can someone point me in the right direction.

Thank you all for all of your help, it has been interesting Adjusting to this new chip.

Re: Simple Timer Interupt.

newguy — Fri, 30 Nov 2007 22:54:54 GMT

I am using the 52223 EVB and this is what I have come up with but it does not work. ANY IDEAS

__interrupt__ void handler_pit0_int (void);

void InitializeInterrupt(void)
{

MCF_PIT0_PCSR |= MCF_PIT_PCSR_OVW;
    /* Update PMR and then enable timer */
    MCF_PIT0_PMR = MCF_PIT_PMR_PM(0x7c);
    MCF_PIT0_PCSR = MCF_PIT_PCSR_PRE(0x5) |
                    MCF_PIT_PCSR_PIE      |
                    MCF_PIT_PCSR_RLD      |
                    MCF_PIT_PCSR_EN;

    /* PIT1 disabled (PCSR1[EN]=0) */
    MCF_PIT1_PCSR = 0;
}

/////////////////////////////////////////////////////////////////////////
void
mcf5xxx_irq_enable (void)
{
asm_set_ipl(0);
}
/********************************************************************/
void
mcf5xxx_irq_disable (void)
{
asm_set_ipl(7);
}
/********************************************************************/

/////////////////////////////////////////////////////////////////////
__interrupt__ void handler_pit0_int (void)
{

//Interrupt code
/* Clear interrupt IF*/
    MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;

}

Re: Simple Timer Interupt.

SimonMarsden_de — Fri, 30 Nov 2007 23:43:16 GMT

Hi

Did you also remember to configure the interrupt controller? You need to do two things:

(1) Configure the individual interrupt for the PIT, ICR55. For example:

   MCF_INTC0_ICR55 = MCF_INTC_ICR_IL(0x1) |
                                       MCF_INTC_ICR_IP(0x1);

(2) Enable the interrupt by clearing its bit in the IMRH/IMRL mask registers. You also need to clear the mask-all bit:

    MCF_INTC0_IMRH &= ~(1 << 55);
    MCF_INTC0_IMRL &= ~1;

You also need to make sure that the correct entry in the exception table points at your interrupt service routine, and that the vector base register (VBR) points to the base of the table.

Hope this helps

Simon