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    <title>topic Re: DMA Priority in ColdFire/68K Microcontrollers and Processors</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/DMA-Priority/m-p/166036#M5773</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;MCF52110 ColdFire® Integrated&lt;BR /&gt;Microcontroller Reference Manual﻿&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;16.4.3.1 Channel Prioritization&lt;BR /&gt;The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel&lt;BR /&gt;3 having the lowest) or in an order determined by DCRn[BWC].﻿&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 12 Sep 2011 07:00:50 GMT</pubDate>
    <dc:creator>TomE</dc:creator>
    <dc:date>2011-09-12T07:00:50Z</dc:date>
    <item>
      <title>DMA Priority</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/DMA-Priority/m-p/166035#M5772</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have MCF52100CAE66 MCU. If I set for DMA0 and DMA2&amp;nbsp; identical data source (for example, URB0) who will have high priority - DMA0 or DMA2?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 10 Sep 2011 18:47:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/DMA-Priority/m-p/166035#M5772</guid>
      <dc:creator>Dekabrist</dc:creator>
      <dc:date>2011-09-10T18:47:34Z</dc:date>
    </item>
    <item>
      <title>Re: DMA Priority</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/DMA-Priority/m-p/166036#M5773</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;MCF52110 ColdFire® Integrated&lt;BR /&gt;Microcontroller Reference Manual﻿&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;16.4.3.1 Channel Prioritization&lt;BR /&gt;The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel&lt;BR /&gt;3 having the lowest) or in an order determined by DCRn[BWC].﻿&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Sep 2011 07:00:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/DMA-Priority/m-p/166036#M5773</guid>
      <dc:creator>TomE</dc:creator>
      <dc:date>2011-09-12T07:00:50Z</dc:date>
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