ColdFire/68K Microcontrollers and ProcessorsのトピックRe: Watchdog doesn't Reset (MCF52259)

Watchdog doesn't Reset (MCF52259)

Patrick_123 — Fri, 09 Sep 2011 21:23:38 GMT

Hello

Im using the watchdog on the MCF52259.

I've generated the simple code with processor expert to reset the CPU with WD:

#define WDog_Enable() (setReg16Bit(WCR,EN),ERR_OK)

byte WDog_Clear(void)
{
if (!testReg16Bits(WCR,1)) {         /* Is WDT disabled? */
    return ERR_DISABLED;               /* If yes then error */
}
setReg16(WSR,0x5555);                /* Write first key */
setReg16(WSR,0xAAAA);                /* Write second key */
return ERR_OK;                       /* OK */
}

I've tested the watchdog function with a simple for loop, which is entered if I press a button. After entering the loop for specified time, the Watchdog resets the CPU and everything works fine.

Now I've implemented it and did some tests (EMC and that stuff). During surge-tests the CPU always hang up, so I've implemented the WD like written before. But the problem is, that the WD doesn't reset the CPU although it works fine on my desk (tested like written above with for-loop). Is there anything else to care about? Is the WD disabled if there is any other interrupt which may occure?

If I reset the CPU via RSTIN-Pin in this hang-up-state it restarts works fine again.

Thanks for help.

Patrick

Re: Watchdog doesn't Reset (MCF52259)

TomE — Mon, 12 Sep 2011 06:37:37 GMT

> During surge-tests the CPU always hang up ... But the problem is, that the WD doesn't reset the CPU

Your "surge test" is doing something nasty to the CPU. Nasty enough that the Watchdog is being reset or disabled by the "surge". That is to be expected. The "surge" must be exceeding some maximum rating for the CPU chip. It might even be bad enough to be able to damage the CPU.

If you require your design to be able to withstand the type of "surges" you're subjecting it to, then you either need to harden the board design to protect the CPU from them (so it keeps going) or you may need to add an external hardware watchdog chip.

Tom

Re: Watchdog doesn't Reset (MCF52259)

Patrick_123 — Mon, 12 Sep 2011 14:41:15 GMT

Of course there has to be some effect that the CPU stops running. But after the surge-test all voltages are at specified level, XTAL is running but nothing happens ... there has to be something else in the CPU that doesn't work correct although everything else is working at normal level.

Some other information: I've made this test a lot of times (10+) and no component was destroyed till now. So that's one more reason, I believe, it has to do something with the CPU, because if i I reset it through RST-Pin it works great. So anything else except the CPU, works correct.

Re: Watchdog doesn't Reset (MCF52259)

ProcessorExpert — Mon, 12 Sep 2011 17:29:24 GMT

Hello,

could you please post here the PE project that leads you to getting the problem?

best regards
Vojtech Filip
Processor Expert Support Team

Re: Watchdog doesn't Reset (MCF52259)

Patrick_123 — Mon, 12 Sep 2011 17:54:34 GMT

That's the PE generated init-code:

void PE_low_level_init(void)
{
/* Initialization of the SCM module */
/* CWCR: CWE=0,CWRI=0,CWT=0,CWTA=0,CWTAVAL=1,CWTIF=1 */
setReg8(CWCR, 0x03);
/* CWSR: CWSR=0x55 */
setReg8(CWSR, 0x55);
/* CWSR: CWSR=0xAA */
setReg8(CWSR, 0xAA);
/* CWCR: CWE=0,CWRI=0,CWT=0,CWTA=0,CWTAVAL=0,CWTIF=0 */
setReg8(CWCR, 0x00);
/* MPARK: BCR24BIT=0 */
clrReg32Bits(MPARK, 0x01000000UL);
/* DMAREQC: DMAC3=0,DMAC2=0,DMAC1=0,DMAC0=0 */
clrReg32Bits(DMAREQC, 0xFFFFUL);
/* MPARK: M2_P_EN=0,M3_PRTY=3,M2_PRTY=2,M0_PRTY=0,M1_PRTY=1,FIXED=0,TIMEOUT=0,PRKLAST=0,LCKOUT_TIME=0 */
clrSetReg32Bits(MPARK, 0x021E7F00UL, 0x00E10000UL);
/* MPR: MPR=3 */
clrSetReg8Bits(MPR, 0x0C, 0x03);
/* PACR0: LOCK1=0,ACCESS_CTRL1=0 */
clrReg8Bits(PACR0, 0xF0);
/* PACR1: LOCK0=0,ACCESS_CTRL0=0 */
clrReg8Bits(PACR1, 0x0F);
/* PACR2: LOCK1=0,ACCESS_CTRL1=0,LOCK0=0,ACCESS_CTRL0=0 */
setReg8(PACR2, 0x00);
/* PACR3: LOCK1=0,ACCESS_CTRL1=0 */
clrReg8Bits(PACR3, 0xF0);
/* PACR4: LOCK1=0,ACCESS_CTRL1=0,LOCK0=0,ACCESS_CTRL0=0 */
setReg8(PACR4, 0x00);
/* PACR5: LOCK1=0,ACCESS_CTRL1=0 */
clrReg8Bits(PACR5, 0xF0);
/* PACR6: LOCK1=0,ACCESS_CTRL1=0,LOCK0=0,ACCESS_CTRL0=0 */
setReg8(PACR6, 0x00);
/* PACR7: LOCK1=0,ACCESS_CTRL1=0,LOCK0=0,ACCESS_CTRL0=0 */
setReg8(PACR7, 0x00);
/* PACR8: LOCK1=0,ACCESS_CTRL1=0,LOCK0=0,ACCESS_CTRL0=0 */
setReg8(PACR8, 0x00);
/* PACR10: LOCK1=0,ACCESS_CTRL1=0 */
clrReg8Bits(PACR10, 0xF0);
/* GPACR0: LOCK=0,ACCESS_CTRL=0 */
clrReg8Bits(GPACR0, 0x8F);
/* GPACR1: LOCK=0,ACCESS_CTRL=0 */
clrReg8Bits(GPACR1, 0x8F);
/* Initialization of the PowerManagement module */
/* LPCR: LPMD=0 */
clrReg8Bits(LPCR, 0xC0);
/* LPICR: ENBSTOP=0,XLPM_IPL=0 */
clrReg8Bits(LPICR, 0xF0);
/* PPMRH: CDUSB=1,CDCFM=0,CDPWM=0,CDGPT=0,CDADC=0,CDPIT1=0,CDPIT0=0,CDEPORT=0,CDGPIO=0 */
clrSetReg32Bits(PPMRH, 0x0B9BUL, 0x1000UL);
/* PPMRL: CDFEC=0,CDINTC1=0,CDINTC0=0,CDDTIM3=0,CDDTIM2=0,CDDTIM1=0,CDDTIM0=0,CDRTC=0,CDI2C1=0,CDQSPI=0,CDI2C0=0,CDUART2=0,CDUART1=0,CDUART0=0,CDDMA=0,CDMINIBUS=0,CDG=0 */
clrReg32Bits(PPMRL, 0x0027FEFAUL);
/* IPSBMT: BME=1,BMT=0 */
clrSetReg8Bits(IPSBMT, 0x07, 0x08);
/* Initialization of the ResetController module */
/* ResetController_RCR: SOFTRST=0,FRCRSTOUT=0,??=0,LVDF=1,LVDIE=0,LVDRE=1,??=0,LVDE=1 */
setReg8(ResetController_RCR, 0x15);
/* Initialization of the CCM module */
/* CCR: LOAD=0 */
clrReg16Bits(CCR, 0x8000U);
/* IMRL0: MASKALL=0 */
clrReg32Bits(IMRL0, 0x01UL);         /* Disable masking of all interrupts of the INTC0 device */
/* IMRL1: MASKALL=0 */
clrReg32Bits(IMRL1, 0x01UL);         /* Disable masking of all interrupts of the INTC1 device */
/* SCM_RAMBAR: BA=0x2000,??=0,??=0,??=0,??=0,??=0,??=0,BDE=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
setReg32(SCM_RAMBAR, 0x20000200UL);

/* GPTSCR1: GPTEN=0,??=0,??=0,TFFCA=0,??=0,??=0,??=0,??=0 */
setReg8(GPTSCR1, 0x00);
/* GPTIE: CI1=0,CI0=0 */
clrReg8Bits(GPTIE, 0x03);
/* GPTIOS: IOS1=1,IOS0=1 */
setReg8Bits(GPTIOS, 0x03);
/* GPTCTL1: OM1=0,OL1=0,OM0=0,OL0=0 */
clrReg8Bits(GPTCTL1, 0x0F);
/* GPTCTL2: EDG1B=0,EDG1A=0,EDG0B=0,EDG0A=0 */
clrReg8Bits(GPTCTL2, 0x0F);
/* ICR044: IL=4,IP=3 */
clrSetReg8Bits(ICR044, 0x1C, 0x23);
/* ICR045: IL=4,IP=3 */
clrSetReg8Bits(ICR045, 0x1C, 0x23);
/* ICR008: IL=0,IP=0 */
clrReg8Bits(ICR008, 0x3F);
/* ICR048: IL=0,IP=0 */
clrReg8Bits(ICR048, 0x3F);
/* PTHPAR: PTHPAR1=0 */
clrReg16Bits(PTHPAR, 0x0CU);
/* IMRL0: INT_MASK22=0,INT_MASK17=1,INT_MASK8=1 */
clrSetReg32Bits(IMRL0, 0x00400000UL, 0x00020100UL);
/* IMRH0: INT_MASK48=1,INT_MASK45=0,INT_MASK44=0 */
clrSetReg32Bits(IMRH0, 0x3000UL, 0x00010000UL);
RTC1_Init();
PWM_Backlight_Init();
PWM_Contrast_Init();
PWM_U_Out_Init();
PWM_I_Out_Init();
AD1_Init();
Flow_Impulse_Init();
TimerInt_Init();
TimerInt_100m_Init();

/* ### WatchDog "WDog" init code ... */
/* WMR: WM=0x243E */
setReg16(WMR, 0x243EU);
/* Common peripheral initialization - ENABLE */
/* PWMSDN: IF=0,IE=0,RESTART=0,LVL=0,??=0,PWM7IN=0,PWM7IL=0,SDNEN=0 */
setReg8(PWMSDN, 0x00);
/* PWME: PWME7=1,PWME5=1,PWME3=1,PWME1=1 */
setReg8Bits(PWME, 0xAA);
/* GPTSCR1: GPTEN=1,??=0,??=0,TFFCA=0,??=0,??=0,??=0,??=0 */
setReg8(GPTSCR1, 0x80);              /* Enable GPT module */
__EI(0);                             /* Enable interrupts of the given priority level */
}

I hope that's what you are looking for. The WD is enabled in an other section of the code, which is exectued right after the low-level-init.

Thanks for help.

Patrick