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    <title>topic Re: MCF5272, 32MB SDRAM and VxWorks. in ColdFire/68K Microcontrollers and Processors</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165413#M5665</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;BLOCKQUOTE&gt;&lt;HR /&gt;japp wrote:&lt;BR /&gt;&lt;P&gt;Hello, we have designed a board with 32 MB (32x)of SDRAM (2 IC of 16x in parallel) and MCF5272. We have problem when VxWorks is booting and shows an access error or freezes. We have this problem in almost 50 % of the boards.The SDRAM IC's are Micron and we use recommended configuration in MCF5272 datasheet. We have designed another board with the same micro and operating system but SDRAM in x16 configuration without problems.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Anybody has the same problem ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;Joaquin&lt;HR /&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Had something similar just this week. MCF5329 with 32-bit-wide SDRAM.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Some of the boards would freeze on boot, get kicked by the watchdog and then work OK after that.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The loader in FLASH copies itself to SDRAM and then jumps to it.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The debugger showed an "illegal instruction trap"on the SECOND instrucxtion fetched from SDRAM.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The debugger showed that of all the data copied from FLASH to SDRAM, 16 32-bit words corresponding to the first cache line fetched by the CPU had their lower 16 bits corrupted.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We were following the SDRAM and Freescale's specs, including the "&amp;gt; 100us wait after clock applied", the two "auto precharge" and the SDRAM chip programming steps.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The fix was to READ aat least one word from the SDRAM before writing to it. We don't know what the problem is, but I'd guess that the SDRAM or SDRAM controller needs "some sort of extra precharge-type operation" after initialisation that writing (and I'd guess the refresh cycles) just doesn't provide.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;Does your startup ROM code do a FLASH checksum and an SDRAM test on startup and report the results anywhere?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&amp;nbsp;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 09 Jan 2010 13:51:51 GMT</pubDate>
    <dc:creator>TomE</dc:creator>
    <dc:date>2010-01-09T13:51:51Z</dc:date>
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      <title>MCF5272, 32MB SDRAM and VxWorks.</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165411#M5663</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, we have designed a board with 32 MB (32x)of SDRAM (2 IC of 16x in parallel) and MCF5272. We have problem when VxWorks is booting and shows an access error or freezes. We have this problem in almost 50 % of the boards.The SDRAM IC's are Micron and we use recommended configuration in MCF5272 datasheet. We have designed another board with the same micro and operating system but SDRAM in x16 configuration without problems.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Anybody has the same problem ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;SPAN&gt;Joaquin&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Jan 2010 16:01:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165411#M5663</guid>
      <dc:creator>japp</dc:creator>
      <dc:date>2010-01-05T16:01:58Z</dc:date>
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      <title>Re: MCF5272, 32MB SDRAM and VxWorks.</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165412#M5664</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Joaquin, Here is a copy of my posting a year ago:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I transfered the 5271 EVB SDRAM&amp;nbsp; (MT48LC4M16A2 x2) to a PCB design using the 5271 QFP.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The driver for the 5271EVB BGA&amp;nbsp; works great, but on the new design&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;it will only read/write the 1st, 3rd, 5th and 7th 1MByte blocks correctly.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Once CPU A20 (0x00100000) is set high (A20=A10/Precharge), I can't read/write these address's.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The only differance is the QFP and BGA so I suspect there is a mask issue.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The QFP works with a single 8Mbyte device but not two 8Mbyte devices on a 32bit bus.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Any ideas?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Rick Stelzer&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;rstelzer@rletech.com&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I've never had a reply to my similiar issue. We have been stuck with single 8M sdram on a 16 bit bus.&lt;/P&gt;&lt;P&gt;We are looking at increasing the size to 16M and stay on the 16 bit bus but we are nervous over&lt;/P&gt;&lt;P&gt;the driver change.&lt;/P&gt;&lt;P&gt;Rick&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 08 Jan 2010 05:37:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165412#M5664</guid>
      <dc:creator>Cactus</dc:creator>
      <dc:date>2010-01-08T05:37:47Z</dc:date>
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    <item>
      <title>Re: MCF5272, 32MB SDRAM and VxWorks.</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165413#M5665</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;BLOCKQUOTE&gt;&lt;HR /&gt;japp wrote:&lt;BR /&gt;&lt;P&gt;Hello, we have designed a board with 32 MB (32x)of SDRAM (2 IC of 16x in parallel) and MCF5272. We have problem when VxWorks is booting and shows an access error or freezes. We have this problem in almost 50 % of the boards.The SDRAM IC's are Micron and we use recommended configuration in MCF5272 datasheet. We have designed another board with the same micro and operating system but SDRAM in x16 configuration without problems.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Anybody has the same problem ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;Joaquin&lt;HR /&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Had something similar just this week. MCF5329 with 32-bit-wide SDRAM.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Some of the boards would freeze on boot, get kicked by the watchdog and then work OK after that.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The loader in FLASH copies itself to SDRAM and then jumps to it.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The debugger showed an "illegal instruction trap"on the SECOND instrucxtion fetched from SDRAM.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The debugger showed that of all the data copied from FLASH to SDRAM, 16 32-bit words corresponding to the first cache line fetched by the CPU had their lower 16 bits corrupted.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We were following the SDRAM and Freescale's specs, including the "&amp;gt; 100us wait after clock applied", the two "auto precharge" and the SDRAM chip programming steps.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The fix was to READ aat least one word from the SDRAM before writing to it. We don't know what the problem is, but I'd guess that the SDRAM or SDRAM controller needs "some sort of extra precharge-type operation" after initialisation that writing (and I'd guess the refresh cycles) just doesn't provide.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;Does your startup ROM code do a FLASH checksum and an SDRAM test on startup and report the results anywhere?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&amp;nbsp;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 09 Jan 2010 13:51:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165413#M5665</guid>
      <dc:creator>TomE</dc:creator>
      <dc:date>2010-01-09T13:51:51Z</dc:date>
    </item>
    <item>
      <title>Re: MCF5272, 32MB SDRAM and VxWorks.</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165414#M5666</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;First, thank you both&amp;nbsp;for your help.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Rick, we have another MCF5272 board and we use Micron MT48LC32M16A2 using a 16x bus without problems.&amp;nbsp;I think you can use the same board to test the new configuration. We know MCF5272 have an errata using 32x bus for 256 Mbit but we are using 128 Mbit:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;/FONT&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;"The SDRAM configuration using two 16-bit-wide, 256-Mbit SDRAM chips does not work. There is an&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;error in the page mode logic that prevents the SDRAM controller from correctly tracking which pages are currently open when using this configuration. All other SDRAM configurations documented in the 5272 user’s manual work correctly and are unaffected by this errata."&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;TomE, the problem is similar but I took a look on MCF5329 and I think the SDRAM controllers of MCF5272 and MCF5329 are quite different. We have a first program (called Bootloader) always running right and it is when this program load the operating system VxWorks when the random errors appear on some boards. The operating system uses more resources and SDRAM intensively.&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;Thank you anyway.&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;We have&amp;nbsp;SDRAM initialization as described in the manual:&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="Times New Roman"&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="Times New Roman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;"Each SDRAM requires an initialization sequence before it can be accessed. After power up, the SDRAM&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="Times New Roman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;requires a certain time (100 µS) before it can accept the first command of the initialization procedure. After&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="Times New Roman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;this time, one &lt;FONT size="2"&gt;&lt;FONT size="2"&gt;PRECHARGE ALL&lt;/FONT&gt;&lt;/FONT&gt; command and eight &lt;FONT size="2"&gt;&lt;FONT size="2"&gt;REFRESH&lt;/FONT&gt;&lt;/FONT&gt; commands are required. After initialization,&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;an &lt;FONT size="2"&gt;&lt;FONT size="2"&gt;INITIATE LOAD REGISTER SET&lt;/FONT&gt;&lt;/FONT&gt; command is executed, which writes the SDRAM configuration into the&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;SDRAM device mode register.&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;EM&gt;&lt;FONT face="Arial"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/EM&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;SDRAM mode register data is transferred on the address signals, so all SDRAM devices are configured&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;simultaneously.&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;EM&gt;&lt;FONT face="Arial"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/EM&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;Initialization is enabled by setting SDCR[INIT] and performing a dummy write to the SDRAM address&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;space. The SDRAM controller executes the required &lt;FONT size="2"&gt;&lt;FONT size="2"&gt;PRECHARGE&lt;/FONT&gt;&lt;/FONT&gt; and &lt;FONT size="2"&gt;&lt;FONT size="2"&gt;REFRESH&lt;/FONT&gt;&lt;/FONT&gt; commands and&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;automatically loads the mode register, which configures the SDRAM as follows:&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;• SDRAM internal burst is always disabled.&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;• CAS latency is defined by SDTR[CLT].&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;EM&gt;&lt;FONT face="Arial"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/EM&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;&lt;EM&gt;SDCR[ACT] is set after initialization."&lt;/EM&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;EM&gt;&lt;FONT face="Arial"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/EM&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P align="left"&gt;&lt;FONT face="TimesNewRoman"&gt;&lt;EM&gt;&lt;FONT face="Arial"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/EM&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Jan 2010 19:07:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165414#M5666</guid>
      <dc:creator>japp</dc:creator>
      <dc:date>2010-01-13T19:07:42Z</dc:date>
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    <item>
      <title>Re: MCF5272, 32MB SDRAM and VxWorks.</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165415#M5667</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Did you ever find out what the problem was and find a fix?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We have had two more problems with the SDRAM since my first answer to your post.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The first one was "random corruptions" that showed up on the video every now and then. This was lucky, as without literally SEEING the memory corruptions it would have been a lot harder to track down.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The first one is summarised in my post "&lt;STRONG&gt;&lt;FONT size="2"&gt;MCF5329 with random SDRAM 1k "bit rot" corruptions"&lt;/FONT&gt;&lt;/STRONG&gt; here:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.freescale.com/message/66587#66587" title="https://community.freescale.com/message/66587#66587"&gt;https://community.freescale.com/message/66587#66587&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;That one could be related to your problem. We had a "small" design without bus termination requiring low drive strength from the SDRAM controller. This was the default setup for the MCF5235 in our previous design, but the MCF5329 unexpectedly defaults to "high drive strength" on the SDRAM pins (only, the rest are lower strength) and the spikes and overshoots were too much for the SDRAM chip. Make sure your drive strength setup matches your hardware design - and check ALL the signals with a good oscilloscope too.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Our current SDRAM problem is one that causes intermittent power-on failures, detailed in another post.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 18 Sep 2010 14:52:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5272-32MB-SDRAM-and-VxWorks/m-p/165415#M5667</guid>
      <dc:creator>TomE</dc:creator>
      <dc:date>2010-09-18T14:52:24Z</dc:date>
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