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    <title>topic Does the MCF52233 have a cache? in ColdFire/68K Microcontrollers and Processors</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Does-the-MCF52233-have-a-cache/m-p/163944#M5457</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;In the MCF52235RM (reference manual), page 65, it says that the device has a 16 byte instruction cache.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;On a couple pages earlier, they talk about the V2 core having a three 32-bit location instruction buffer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Does anyone know if there is a 16 byte instruction cache?&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 14 Nov 2007 17:08:57 GMT</pubDate>
    <dc:creator>Harjit</dc:creator>
    <dc:date>2007-11-14T17:08:57Z</dc:date>
    <item>
      <title>Does the MCF52233 have a cache?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Does-the-MCF52233-have-a-cache/m-p/163944#M5457</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;In the MCF52235RM (reference manual), page 65, it says that the device has a 16 byte instruction cache.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;On a couple pages earlier, they talk about the V2 core having a three 32-bit location instruction buffer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Does anyone know if there is a 16 byte instruction cache?&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 14 Nov 2007 17:08:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Does-the-MCF52233-have-a-cache/m-p/163944#M5457</guid>
      <dc:creator>Harjit</dc:creator>
      <dc:date>2007-11-14T17:08:57Z</dc:date>
    </item>
    <item>
      <title>Re: Does the MCF52233 have a cache?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Does-the-MCF52233-have-a-cache/m-p/163945#M5458</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hi, Harjit,&lt;BR /&gt;&lt;BR /&gt;The MCF5223x does not have an instruction cache.&amp;nbsp; This is the case for all ColdFire devices that do not have an external bus.&amp;nbsp; WIthout an external bus, there is no use for a cache as all the memories are already on-chip.&lt;BR /&gt;&lt;BR /&gt;However, all V2 ColdFire devices do have an instruction buffer or FIFO between the instruction fetch pipeline and the operand execution pipeline.&amp;nbsp; This is not a cache.&amp;nbsp; It is just a way to allow the core to buffer instructions fetches and minimize potential stalls (waiting for instructions to be fetched).&lt;BR /&gt;&lt;BR /&gt;-mnorman&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 17 Nov 2007 02:04:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Does-the-MCF52233-have-a-cache/m-p/163945#M5458</guid>
      <dc:creator>mnorman</dc:creator>
      <dc:date>2007-11-17T02:04:01Z</dc:date>
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