ColdFire/68K Microcontrollers and ProcessorsのトピックRe: CPLD problem with M54455EVB

CPLD problem with M54455EVB

simath — Fri, 09 Nov 2007 13:59:53 GMT

I just received my M54455EVB and am having a problem accessing the CPLD as described in the User's Manual. I'm using a simple "Hello World" console app. test for this. I can access the FPGA registers at 0x0900_0000 as described in the manual (getting the expected values), but get only 0xFF for the entire mapped range for the CPLD (0x0800_0000). The M54455EVB_RAM.cfg file contents are actually getting written to the CS registers (verified by a Register dump), as expected (see below). I'm not sure the values are correct for the CPLD mode register (the manual says it should have BYTE access only).

Can anyone out there with an EVB try to perform a read from the CPLD registers and see if the results are as expected (i.e. something other than 0xFF)?

Is it possible to get access to the CPLD sources (I'm quite fluent at Xilinx builds)?

;Init CS2 - CPLD @ 0x0800_0000
writemem.l 0xFC008018 0x08000000;
writemem.l 0xFC008020 0x00000000;
writemem.l 0xFC00801C 0x00000001;

;Init CS3 - FPGA @ 0x0900_0000
writemem.l 0xFC008024 0x09000000;
writemem.l 0xFC00802C 0x00000020;
writemem.l 0xFC008028 0x00000001;

Re: CPLD problem with M54455EVB

kmahan — Sat, 10 Nov 2007 10:40:17 GMT

Are you able to write to the CPLD LEDS register (0x08000005 -- byte access) and illuminate the associated CPLD leds? You should be able to read back the lower 6 bits that you wrote.

I don't currently have a board in front of me to test this out but I will in the morning.

Are you using dBug or uBoot? Can you just bang the associated mem addresses from whichever of those you're using?

--Kurt

Re: CPLD problem with M54455EVB

simath — Sat, 10 Nov 2007 14:16:08 GMT

CPLD access works fine in uBoot (although it does 32-bit accesses). I can't get it to work with CodeWarrior 7.0 though. That's using the BDM channel though, not doing CPU-based accesses. The FPGA register access works fine via BDM in CW (can control the 7-seg., read version, etc.). I can turn the CPLD LEDs on/off using uBoot. I suspect that I could add to the default CW console app. to do program I/O and that access would work fine too (like with uBoot). Anyway, it doesn't really matter. As seen in the other post, I thought the USB issue was related to the CPLD problem (I thought maybe the SW1 settings weren't getting in properly and the the ULPI PHY was being held in reset). You solved the USB problem with the new kernel build... Thanks again!

My board shipped with a different JP904 setting than the default listed (2-3 not 1-2). I see from the schematics this is related to a BDM clock signal - changing that didn't fix the CPLD access problem though. Just curious as to if this JP904 setting matters and I should set it back to the doc. default?

Re: CPLD problem with M54455EVB

kmahan — Sun, 11 Nov 2007 01:19:26 GMT

For BDM usage the jumpers should be:

JP903 2-3 ("Debug Mode Selection" Table 10 in the EVB User Manual)
JP904 1-2 ("TCLK/PSTCLK Routing Control" Table 11 in the EVB User Manual)

The board assembly doc I've got says the boards should be delivered with the above configuration. I've not received any "final box" boards though. Maybe Michael Norman can comment.

Michael can probably also comment on the CW part of your question. As you've figured out I do the Linux parts -- I'm not familiar with using CW on this board. So I can't speak to how the CW environment sets things up.

Re: CPLD problem with M54455EVB

simath — Sun, 11 Nov 2007 07:08:15 GMT

The CW .cfg files are incorrect. CPLD access needs wait-states and setup/hold delays. The correct values are below (with some added comments). This fixed the problem...

;Init CS0 - Flash0 @ 0x0400_0000
; CSAR0 = 0x0400 Base Address
; CSMR0 = 8*64k Blocks, VALID
; CSCR0 = 4 W/S, Auto-Ack, 8-Bit
writemem.l 0xFC008000 0x04000000;
writemem.l 0xFC008008 0x00001140;
writemem.l 0xFC008004 0x00070001;

;Init CS1 - Flash1 @ 0x0000_0000
; CSAR0 = 0x0000 Base Address
; CSMR0 = 512*64k Blocks, VALID
; CSCR0 = 3 W/S, Auto-Ack, 8-Bit, Byte-Enable
writemem.l 0xFC00800C 0x00000000;
writemem.l 0xFC008014 0x00000D60;
writemem.l 0xFC008010 0x01FF0001;

;Init CS2 - CPLD @ 0x0800_0000
; CSAR0 = 0x0800 Base Address
; CSMR0 = 8*64k Blocks, VALID
; CSCR0 = Address Setup Delay = 4, R/W Address Hold = 4, 4 W/S, Auto-Ack, 8-Bit
writemem.l 0xFC008018 0x08000000;
writemem.l 0xFC008020 0x003F1140;
writemem.l 0xFC00801C 0x00070001;

;Init CS3 - FPGA @ 0x0900_0000
; CSAR0 = 0x0800 Base Address
; CSMR0 = 8*64k Blocks, VALID
; CSCR0 = 32-Bit, Byte-Enable
writemem.l 0xFC008024 0x09000000;
writemem.l 0xFC00802C 0x00000020;
writemem.l 0xFC008028 0x00070001;