<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>ColdFire/68K Microcontrollers and ProcessorsのトピックMCF5216 internal flash security and internal SRAM addressing</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5216-internal-flash-security-and-internal-SRAM-addressing/m-p/154993#M4383</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi, I need&amp;nbsp;urgent help here.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;we use internal flash for all the code&amp;nbsp;also need to adress external SRAM and other peripheral devices residing on external bus port.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I need to secure the internal flash to protect the code and then realized the external SRAM and other devices on data bus.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;contact tech support and the reply through email is that it can be done.&amp;nbsp;I was told that after the single chip mode boot up, I need to configure the bus&amp;nbsp;pins from GPIO back to primary function. However I cannot find any way to configure the address pins back to primary function as there&amp;nbsp;are no Port-H, Port-G pin assignemnt registers.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;thanks.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 12 Oct 2007 22:55:20 GMT</pubDate>
    <dc:creator>JackD</dc:creator>
    <dc:date>2007-10-12T22:55:20Z</dc:date>
    <item>
      <title>MCF5216 internal flash security and internal SRAM addressing</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5216-internal-flash-security-and-internal-SRAM-addressing/m-p/154993#M4383</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi, I need&amp;nbsp;urgent help here.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;we use internal flash for all the code&amp;nbsp;also need to adress external SRAM and other peripheral devices residing on external bus port.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I need to secure the internal flash to protect the code and then realized the external SRAM and other devices on data bus.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;contact tech support and the reply through email is that it can be done.&amp;nbsp;I was told that after the single chip mode boot up, I need to configure the bus&amp;nbsp;pins from GPIO back to primary function. However I cannot find any way to configure the address pins back to primary function as there&amp;nbsp;are no Port-H, Port-G pin assignemnt registers.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;thanks.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 12 Oct 2007 22:55:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5216-internal-flash-security-and-internal-SRAM-addressing/m-p/154993#M4383</guid>
      <dc:creator>JackD</dc:creator>
      <dc:date>2007-10-12T22:55:20Z</dc:date>
    </item>
    <item>
      <title>Re: MCF5216 internal flash security and External SRAM addressing</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5216-internal-flash-security-and-internal-SRAM-addressing/m-p/154994#M4384</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;sorry, some mistakes above.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;Hi, I need&amp;nbsp;urgent help here.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;we use internal flash for all the code&amp;nbsp;also need to adress external SRAM and other peripheral devices residing on external bus port.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I need to secure the internal flash to protect the code and then realized the external SRAM and other devices on data bus &lt;FONT color="#ff0000"&gt;CANNOT&lt;/FONT&gt; be addressed.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;contact tech support and the reply through email is that it can be done.&amp;nbsp;I was told that after the single chip mode boot up, I need to configure the bus&amp;nbsp;pins from GPIO back to primary function. However I cannot find any way to configure the address pins back to primary function as there&amp;nbsp;are no Port-H, Port-G pin assignemnt registers.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;thanks.&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 13 Oct 2007 00:08:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5216-internal-flash-security-and-internal-SRAM-addressing/m-p/154994#M4384</guid>
      <dc:creator>JackD</dc:creator>
      <dc:date>2007-10-13T00:08:57Z</dc:date>
    </item>
    <item>
      <title>Re: MCF5216 internal flash security and External SRAM addressing</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5216-internal-flash-security-and-internal-SRAM-addressing/m-p/154995#M4385</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi JackD&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;My reply (very late from your post...) just to know if you have solved this problem......&lt;/P&gt;&lt;P&gt;I have the same problem: keep active the external bus for a big SDRAM banks but with internal flash secured from undesiderable BDM access!!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Have you solved?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Have you received a valid hints from Freescale people or from this forums?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance for the reply&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Nov 2009 00:54:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5216-internal-flash-security-and-internal-SRAM-addressing/m-p/154995#M4385</guid>
      <dc:creator>theresources</dc:creator>
      <dc:date>2009-11-27T00:54:24Z</dc:date>
    </item>
  </channel>
</rss>

