<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic MCF537x: continuous transmit with QSPI? in ColdFire/68K Microcontrollers and Processors</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF537x-continuous-transmit-with-QSPI/m-p/154469#M4303</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am trying to use the QSPI to load an FPGA in an application board, so want to transfer a large amount of data as fast as possible.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;My idea was to use QSPI for this, but from reading the manual I am not sure if this is possible at all.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The algorithm I have in mind is:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;- set NEWQP to 0, ENDQP to 0xf (full 16 words to transfer)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- fill transmit RAM with the first 16 words&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- start transfer in wrap-around mode&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- poll for CPTQP changes and, if one word is transferred, write the next word to this free location in transmit RAM&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- when the last wrap-around occured, clear wrap-around mode and set ENDQP to the last location to be transferred (if the number of words is not divisible by 16)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;But I am not sure if writing ENDQP (in the same register as NEWQP) will modify the internal pointer? And, I am a bit puzzled by "Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer." in the Section 28.4.3, "Transfer Delays" - does that mean the Standard delay of 17/(fsys/3) is not sufficient? Furthermore, the Note in the table entry for the CONT bit in QCR[0-15] "In order to keep the chip selects asserted for transfers beyond 16 words, ..." is not clear to me - I can only set one inactive level, which does not help me to set the state of 4 CS bits...&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In case this has already been answered somewhere, please point me to this - I could not find it in the search.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Help would be really appreciated because unfortunately, I have no real test points where I could measure the signals to see what happens in this design.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Wolfgang&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 11 Oct 2007 23:35:34 GMT</pubDate>
    <dc:creator>w_wegner</dc:creator>
    <dc:date>2007-10-11T23:35:34Z</dc:date>
    <item>
      <title>MCF537x: continuous transmit with QSPI?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF537x-continuous-transmit-with-QSPI/m-p/154469#M4303</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am trying to use the QSPI to load an FPGA in an application board, so want to transfer a large amount of data as fast as possible.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;My idea was to use QSPI for this, but from reading the manual I am not sure if this is possible at all.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The algorithm I have in mind is:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;- set NEWQP to 0, ENDQP to 0xf (full 16 words to transfer)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- fill transmit RAM with the first 16 words&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- start transfer in wrap-around mode&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- poll for CPTQP changes and, if one word is transferred, write the next word to this free location in transmit RAM&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- when the last wrap-around occured, clear wrap-around mode and set ENDQP to the last location to be transferred (if the number of words is not divisible by 16)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;But I am not sure if writing ENDQP (in the same register as NEWQP) will modify the internal pointer? And, I am a bit puzzled by "Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer." in the Section 28.4.3, "Transfer Delays" - does that mean the Standard delay of 17/(fsys/3) is not sufficient? Furthermore, the Note in the table entry for the CONT bit in QCR[0-15] "In order to keep the chip selects asserted for transfers beyond 16 words, ..." is not clear to me - I can only set one inactive level, which does not help me to set the state of 4 CS bits...&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In case this has already been answered somewhere, please point me to this - I could not find it in the search.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Help would be really appreciated because unfortunately, I have no real test points where I could measure the signals to see what happens in this design.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Wolfgang&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Oct 2007 23:35:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF537x-continuous-transmit-with-QSPI/m-p/154469#M4303</guid>
      <dc:creator>w_wegner</dc:creator>
      <dc:date>2007-10-11T23:35:34Z</dc:date>
    </item>
    <item>
      <title>Re: MCF537x: continuous transmit with QSPI?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF537x-continuous-transmit-with-QSPI/m-p/154470#M4304</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;By your way with wraparound, you cal poll QWR[CPTQP]:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; - Wait until the QWR[CPTQP] field is changed;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; - Set QAR to address of above completed transmit word;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; - Write QDR with the next 16-bit transmit word;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; - Repeat&amp;nbsp; above operations until end of file.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;For my oppinion, your algorithm is problematic - without notable communication speed improvement.&lt;/DIV&gt;&lt;DIV&gt;Let use standard way without wraparound (derived from NetBurner code and debugged with mcf5270):&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; - Fill next 16 transmit words;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; -&amp;nbsp;Enable the QSPI communication;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; - Wait for finish: either poll QIR[SPIF] or concerned&amp;nbsp;interrupt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; - Repeat above operations until end of file.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Tune the baudrate,&amp;nbsp;'Delay after transfer', 'CS to SCLK', and other parameters&amp;nbsp;according to your FPGA chip datasheet.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Nov 2007 23:34:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF537x-continuous-transmit-with-QSPI/m-p/154470#M4304</guid>
      <dc:creator>admin</dc:creator>
      <dc:date>2007-11-19T23:34:47Z</dc:date>
    </item>
  </channel>
</rss>

