ICS Settings for MCF51QE128

ChrisR109 — Tue, 10 Feb 2009 00:50:47 GMT

Question about the MCF51QE128 clock module (using DEMOQE board):
I have my board configured to run off the external 32kHz crystal, and have set the following registers
ICSC1 = 0x00;
ICSC2 = 0x30;
ICSSC = 0x60;
According to the documentation, my bus speed should be 39.85Mhz, but on the Command window of the debugger I get
Frequency change to ~19029757hz.

Which is correct? Also, what is the highest bus speed I can run at (using external crystal) and still get a standard RS232 baud rate?

Re: ICS Settings for MCF51QE128

admin — Thu, 12 Feb 2009 04:49:10 GMT

The clock init used is not correct.

ICSC2 should be set to 0x02 to enable the external clock - ERCLKEN = 1.

The below code was generated using Processor expert

/* System clock initialization */
/* ICSC1: CLKS=0,RDIV=0,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
setReg8(ICSC1, 0x00);                /* Initialization of the ICS control register 1 */
/* ICSC2: BDIV=0,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=1,EREFSTEN=0 */
setReg8(ICSC2, 0x02);                /* Initialization of the ICS control register 2 */
/* ICSSC: DRST_DRS=1,DMX32=1 */
clrSetReg8Bits(ICSSC, 0x80, 0x60);   /* Initialization of the ICS status and control */
while((ICSSC & 0xC0) != 0x40) {      /* Wait until the FLL switches to Mid range DCO mode *

This is the configuration for generating a 19.922944 Bus clock/39.84588 System clock from a 32.768kHz crystal.

The max bus speed for this device is 25Mhz, The max System clock is 50Mhz. Setting the clock to the max bus speed requires the below configuration.

/* System clock initialization */
/* ICSC1: CLKS=0,RDIV=0,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
setReg8(ICSC1, 0x00);                /* Initialization of the ICS control register 1 */
/* ICSC2: BDIV=0,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=1,EREFSTEN=0 */
setReg8(ICSC2, 0x02);                /* Initialization of the ICS control register 2 */
/* ICSSC: DRST_DRS=2,DMX32=0 */
clrSetReg8Bits(ICSSC, 0x60, 0x80);   /* Initialization of the ICS status and control */
while((ICSSC & 0xC0) != 0x80) {      /* Wait until th

The Baud rate that can be used at this bus clock will depend on the level of error that you can accept to the communication.

Using processor expert you can easily see the generated Baud Rate and the error. 9600, 19200, 38400 baud all are achievable with less than 0.1% error. 57600 baud will have 1.136% error. This is acceptable for most systems. 115200 will have greater than 1.5% error.

Re: ICS Settings for MCF51QE128

thinker — Tue, 18 May 2010 21:49:05 GMT

Actually, that configuration is not correct for a crystal. If you want to use oscillator you have to set bit EREFS in the ICSC2. For example:

ICSC2 = 0x06;

Regards.

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