<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic Re: SDRAM connections MCF5208 in ColdFire/68K Microcontrollers and Processors</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150728#M3884</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Did you resolve the problem?&lt;BR /&gt;I have the same question:&lt;BR /&gt;Coldfire 5208 in 32 bit mode.&lt;BR /&gt;Flash and SDR RAM with 16 bit size.&lt;BR /&gt;Is correct to connect cpu(A1-A21) to Flash[A0-A20]?&lt;BR /&gt;Thanks,&lt;BR /&gt;Miguel.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 04 Dec 2007 00:54:35 GMT</pubDate>
    <dc:creator>Maybar</dc:creator>
    <dc:date>2007-12-04T00:54:35Z</dc:date>
    <item>
      <title>SDRAM connections MCF5208</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150724#M3880</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi at all,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I will develop a board with the mcf5208. &lt;A href="http://freescale.i.lithium.com/i/smilies/16x16_smiley-surprised.gif"&gt;&lt;IMG alt=":smileysurprised:" class="emoticon emoticon-smileysurprised" src="http://freescale.i.lithium.com/i/smilies/16x16_smiley-surprised.gif" title="Smiley Surprised" /&gt;&lt;/A&gt;&lt;/DIV&gt;&lt;DIV&gt;Now I will know how to connect one or two (assembly option)&amp;nbsp;respectively sdrams (K4S281632)&amp;nbsp;to the cpu.&lt;/DIV&gt;&lt;DIV&gt;These signals are clear to me: -1st sdram D16-D31 to dq0-dq15&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; -dqm3 to udqm&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; -dqm2 to ldqm&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; -2nd sdram D0-D15 to dq0-dq15&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; -dqm1 to udqm&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; -dqm0 to ldqm&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;And what's about the address lines and chip selects? &lt;A href="http://freescale.i.lithium.com/i/smilies/16x16_smiley-mad.gif"&gt;&lt;IMG alt=":smileymad:" class="emoticon-smileymad emoticon" src="http://freescale.i.lithium.com/i/smilies/16x16_smiley-mad.gif" title="Smiley Mad" /&gt;&lt;/A&gt;&lt;/DIV&gt;&lt;DIV&gt;Same address lines in 16bit and 32bit?&lt;/DIV&gt;&lt;DIV&gt;One chip select&amp;nbsp;for both modes (16/32bit) or two?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;thx&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;fevernova&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Sep 2007 17:32:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150724#M3880</guid>
      <dc:creator>fevernova</dc:creator>
      <dc:date>2007-09-27T17:32:05Z</dc:date>
    </item>
    <item>
      <title>Re: SDRAM connections MCF5208</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150725#M3881</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hello FeverNova,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I diodn't look up those memory chips. I guess that they are by-16 architecture. Since the ColdFire has byte addressability, then you need to connect the A0 from the mcu to the A1 on the memory, etc. From your description of what you know already, you seem to want to make a 32-bit wide memory from the 2-off x16 parts, that's why you'd connect the D16 to dq0 on the first sdram. Then you say its a assembly option, which puzzled me.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;2 references for you to look at:&lt;/DIV&gt;&lt;DIV&gt;1) Schematic for the MCF5208 eval board, published to the freescale site&lt;/DIV&gt;&lt;DIV&gt;2) FlexBus application note AN2982.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Good luck&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Mark&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Oct 2007 22:40:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150725#M3881</guid>
      <dc:creator>UK_CF_FAE</dc:creator>
      <dc:date>2007-10-08T22:40:26Z</dc:date>
    </item>
    <item>
      <title>Re: SDRAM connections MCF5208</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150726#M3882</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;...let's start new. &lt;IMG alt=":smileysurprised:" class="emoticon emoticon-smileysurprised" id="smileysurprised" src="http://freescale.i.lithium.com/i/smilies/16x16_smiley-surprised.gif" title="Smiley Surprised" /&gt;&lt;/DIV&gt;&lt;DIV&gt;I will use sdram by 16bit architecture (k4s281632I-ui75)&amp;nbsp;and flash (s29gl032a90tfir4)&amp;nbsp;by 16bit architecture.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;So I'll take a full 32bit bus mode for 32bit sdram controller and 32bit for flexbus (dramsel=1).&lt;/DIV&gt;&lt;DIV&gt;As standard memory I will use one 16bit sdram and so I thought I have to connect the sdram to the upper data lines of the sdram controller:&lt;/DIV&gt;&lt;DIV&gt;sdram dq0=cpu d16&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram dq1=cpu d17&lt;/DIV&gt;&lt;DIV&gt;...&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram dq15=cpu d31&lt;/DIV&gt;&lt;DIV&gt;sdram ldqm=cpu sddqm2&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram udqm=cpu sddqm3&lt;/DIV&gt;&lt;DIV&gt;sdram cs=cpu sdcs0&lt;/DIV&gt;&lt;DIV&gt;sdram a0=cpu a0&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram a1=cpu a1&lt;/DIV&gt;&lt;DIV&gt;...&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram a10=cpu sd_a10&lt;/DIV&gt;&lt;DIV&gt;...&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;sdram n.c./a12=cpu a12&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram ba0=cpu a14&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram ba1=cpu a15&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;And here isthe flash connection:&lt;/DIV&gt;&lt;DIV&gt;flash a0=cpu a1&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;flash a1=cpu a2&lt;/DIV&gt;&lt;DIV&gt;...&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;flash n.c./a21=cpu a22&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;flash cs=cpu cs0&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;flash dq0=cpu d16&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;flash dq1=cpu d17&lt;/DIV&gt;&lt;DIV&gt;...&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;flash dq15=cpu d31&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;refer&amp;nbsp;to page 287 (flexbus, data byte alignment) in manual.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;A an assembly option I will use a second sdram by 16bit to built a 32bit architecture by 2x16bit.&lt;/DIV&gt;&lt;DIV&gt;So I take the second sdram and connect it in this way:&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram dq0=cpu d0&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram dq1=cpu d1&lt;/DIV&gt;&lt;DIV&gt;...&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram dq15=cpu d15&lt;/DIV&gt;&lt;DIV&gt;sdram ldqm=cpu sddqm0&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram udqm=cpu sddqm1&lt;/DIV&gt;&lt;DIV&gt;sdram cs=cpu sdcs0&lt;/DIV&gt;&lt;DIV&gt;sdram a0=cpu a0&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram a1=cpu a1&lt;/DIV&gt;&lt;DIV&gt;...&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram a10=cpu sd_a10&lt;/DIV&gt;&lt;DIV&gt;...&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;sdram n.c./a12=cpu a12&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram ba0=cpu a14&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;sdram ba1=cpu a15&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Is it&amp;nbsp; the correct connection?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I hope it is understandable.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;thx, fevernova&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 09 Oct 2007 13:45:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150726#M3882</guid>
      <dc:creator>fevernova</dc:creator>
      <dc:date>2007-10-09T13:45:07Z</dc:date>
    </item>
    <item>
      <title>Re: SDRAM connections MCF5208</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150727#M3883</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Does anybody has an idea?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;best regards...René&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Oct 2007 19:12:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150727#M3883</guid>
      <dc:creator>fevernova</dc:creator>
      <dc:date>2007-10-23T19:12:50Z</dc:date>
    </item>
    <item>
      <title>Re: SDRAM connections MCF5208</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150728#M3884</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Did you resolve the problem?&lt;BR /&gt;I have the same question:&lt;BR /&gt;Coldfire 5208 in 32 bit mode.&lt;BR /&gt;Flash and SDR RAM with 16 bit size.&lt;BR /&gt;Is correct to connect cpu(A1-A21) to Flash[A0-A20]?&lt;BR /&gt;Thanks,&lt;BR /&gt;Miguel.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Dec 2007 00:54:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150728#M3884</guid>
      <dc:creator>Maybar</dc:creator>
      <dc:date>2007-12-04T00:54:35Z</dc:date>
    </item>
    <item>
      <title>Re: SDRAM connections MCF5208</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150729#M3885</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I think so. Refer to 17.3.1.1 Port Sizing in Manual.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Bye&lt;/DIV&gt;&lt;DIV&gt;&lt;B&gt;&lt;FONT face="Helvetica-Bold" size="4"&gt;&lt;/FONT&gt;&lt;/B&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Dec 2007 15:12:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/SDRAM-connections-MCF5208/m-p/150729#M3885</guid>
      <dc:creator>fevernova</dc:creator>
      <dc:date>2007-12-04T15:12:29Z</dc:date>
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