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    <title>ColdFire/68K Microcontrollers and Processors中的主题 MCF52210 ADC Question</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF52210-ADC-Question/m-p/148750#M3653</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi, I just have a question.&lt;BR /&gt;Is it possible to configure the ADC clock to 5Khz?&lt;BR /&gt;I'm using the PLL with frequency at 64MHz and datasheet says that the minimum frequency is 500Khz.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;thanks!&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 24 Oct 2009 01:18:50 GMT</pubDate>
    <dc:creator>Cuozzo</dc:creator>
    <dc:date>2009-10-24T01:18:50Z</dc:date>
    <item>
      <title>MCF52210 ADC Question</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF52210-ADC-Question/m-p/148750#M3653</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi, I just have a question.&lt;BR /&gt;Is it possible to configure the ADC clock to 5Khz?&lt;BR /&gt;I'm using the PLL with frequency at 64MHz and datasheet says that the minimum frequency is 500Khz.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;thanks!&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 24 Oct 2009 01:18:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF52210-ADC-Question/m-p/148750#M3653</guid>
      <dc:creator>Cuozzo</dc:creator>
      <dc:date>2009-10-24T01:18:50Z</dc:date>
    </item>
    <item>
      <title>Re: MCF52210 ADC Question</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF52210-ADC-Question/m-p/148751#M3654</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The data sheet specifies that the ADC clock should be between 100kHz and 5MHz. This means that 5kHz would be outside of the specified operating range.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Furthermore, the ADC clock is generated from the system clock by dividing it down using the DIV value in the (ADC) CTRL2 register. The maximum DIV value is 0x1f - giving a divide of 64 ((DIV + 1)*2). If your system clock is 32MHz (64MHz PLL) then the lowest ADC speed that you can select is 500kHz - to run the ADC slower than that it would be necessary to also run the processor (PLL) slower.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.uTasker.com" rel="nofollow" target="_self"&gt;www.uTasker.com&lt;/A&gt;&lt;BR /&gt;- OS, TCP/IP stack, USB, device drivers and simulator for M521X, M521XX, M5221X, M5222X, M5223X, M5225X. One package does them all - "&lt;EM&gt;Embedding it better...&lt;/EM&gt;"&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 24 Oct 2009 23:48:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF52210-ADC-Question/m-p/148751#M3654</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2009-10-24T23:48:49Z</dc:date>
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