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    <title>ColdFire/68K Microcontrollers and ProcessorsのトピックRe: ColdFire - CISC?</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147386#M3415</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;I stand corrected. I should have looked into the references before relying on old memories.&lt;BR /&gt;&lt;BR /&gt;Thanks for the info, and sorry to confuse things.&lt;BR /&gt;&lt;BR /&gt;---Tom&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 30 Jan 2009 01:12:31 GMT</pubDate>
    <dc:creator>J2MEJediMaster</dc:creator>
    <dc:date>2009-01-30T01:12:31Z</dc:date>
    <item>
      <title>ColdFire - CISC?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147383#M3412</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Hello All,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style=": ; font-family: Arial;"&gt;&lt;SPAN style="color: #000000;"&gt;The Freescale ColdFire is a 68K&lt;/SPAN&gt; &lt;SPAN style="color: #000000;"&gt;architecture&amp;nbsp;microprocessor&lt;/SPAN&gt; &lt;SPAN style="color: #000000;"&gt;manufactured for embedded systems&lt;/SPAN&gt; &lt;SPAN style="color: #000000;"&gt;development ..&lt;SPAN style=": ; font-size: 4;"&gt;&lt;SPAN style="font-size: 3;"&gt;The Motorola 680x0/m68k/68k/68K is a family of 32-bit CISC microprocessor CPUchips&lt;/SPAN&gt; . &lt;SPAN style="font-size: 3;"&gt;Is the ColdFire following a CISC architecture&lt;/SPAN&gt;.?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Jan 2009 16:29:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147383#M3412</guid>
      <dc:creator>admin</dc:creator>
      <dc:date>2009-01-29T16:29:09Z</dc:date>
    </item>
    <item>
      <title>Re: ColdFire - CISC?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147384#M3413</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;ColdFire is derived from the 68K CISC processor, and is therefore CISC. Major difference between ColdFire and the 68K is that the 68K used a fixed-size instruction length, while ColdFire uses a variable-length instruction set to conserve memory.&lt;BR /&gt;&lt;BR /&gt;---Tom&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Jan 2009 21:32:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147384#M3413</guid>
      <dc:creator>J2MEJediMaster</dc:creator>
      <dc:date>2009-01-29T21:32:49Z</dc:date>
    </item>
    <item>
      <title>Re: ColdFire - CISC?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147385#M3414</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;Sorry, but that's not right.&lt;BR /&gt;&lt;BR /&gt;ColdFire and 68K use the same opcode encodings - and hence the same instruction widths - where the same instruction exists in both architectures.&lt;BR /&gt;&lt;BR /&gt;Freescale describe the ColdFire architecture as a 'variable-length reduced instruction set (RISC) architecture'. Standard RISC implementations tend to use a fixed width of 2 or 4 bytes per instruction, (although both PowerPC and ARM slightly muddy that distinction) whereas ColdFire uses 2, 4 or 6 bytes depending on the instruction.&lt;BR /&gt;&lt;BR /&gt;What Freescale actually did when designing ColdFire was to trawl through the 68K instruction set removing overly-complex instructions that were too difficult to implement efficiently in a redesigned RISC-like processor core.&lt;BR /&gt;&lt;BR /&gt;One of the differences between ColdFire and more traditional RISC implementations is that ColdFire supports memory-based operands. You can add a register to a memory location in a single instruction, whereas RISC processors would normally need three (load from memory, add, store back to memory).&lt;BR /&gt;&lt;BR /&gt;The word RISC has a debatable meaning nowadays anyway. The PowerPC is definitely considered as a RISC processor, but it has far more instructions that ColdFire.&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Jan 2009 22:24:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147385#M3414</guid>
      <dc:creator>SimonMarsden_de</dc:creator>
      <dc:date>2009-01-29T22:24:45Z</dc:date>
    </item>
    <item>
      <title>Re: ColdFire - CISC?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147386#M3415</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;I stand corrected. I should have looked into the references before relying on old memories.&lt;BR /&gt;&lt;BR /&gt;Thanks for the info, and sorry to confuse things.&lt;BR /&gt;&lt;BR /&gt;---Tom&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Jan 2009 01:12:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147386#M3415</guid>
      <dc:creator>J2MEJediMaster</dc:creator>
      <dc:date>2009-01-30T01:12:31Z</dc:date>
    </item>
    <item>
      <title>Re: ColdFire - CISC?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147387#M3416</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hello All,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I am confused ,I got reply as CISC as well as RISC .How it can be concluded?&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Jan 2009 14:02:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147387#M3416</guid>
      <dc:creator>admin</dc:creator>
      <dc:date>2009-01-30T14:02:25Z</dc:date>
    </item>
    <item>
      <title>Re: ColdFire - CISC?</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147388#M3417</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;I think it's the wrong question to ask. Asking "is it CISC or RISC?" is akin to asking "is it black or white?" It could be gray, you know.&lt;BR /&gt;CISC and RISC are processor design strategies. A particular design can draw from both of them, and most designs do. And there is no way to measure it in order to say, for example "it's 60% RISC and 40% CISC".&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Jan 2009 14:30:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/ColdFire-CISC/m-p/147388#M3417</guid>
      <dc:creator>admin</dc:creator>
      <dc:date>2009-01-30T14:30:27Z</dc:date>
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