MCF5484 FEC and fast responses

danik — Thu, 13 Jul 2006 23:00:50 GMT

Hello,

we want to develop a FEC driver for the MCF5484 that is able to respond to a special ethernet frame with a latency as low as possible.

We found two possibilities to reduce the latency.
1. Set the GTS flag in the FEC_TCR register to disable transmission of frames. Copy frame to transmit FIFO. Reset GTS flag when special frame was received.

2. Enable FEC interrupt for BABR events and set MAX_FL to 0. This mimic an early receive interrupt (why is there no receive interrupt for the FEC in MCF5484?). But this interrupt is also triggered after the frame was fully received from the bus. It is possible to check the first bytes of the frame and reset the GTS flag if necessary.

Are there any other possibilites to further reduce the receive-transmit-latency? Is there any interrupt source which signals right after the first 16 bytes of the frame are received?

Thank you for your help in advance.

cu
Daniel

Re: MCF5484 FEC and fast responses

mnorman — Mon, 17 Jul 2006 22:46:48 GMT

On the MCF547x/8x devices, the FEC does not have a dedicated DMA. Instead, the multichannel DMA is used with custom tasks for the FEC. The FEC incorportates a set of FIFOs that are the buffers between the FEC and the DMA. Their is no FEC Rx interrupt, it is intended that the DMA FEC-Rx task interrupt be used instead. However, it is possible for the CPU to directly interface with the FEC FIFOs. The Rx FIFO status and pointer registers would have to be monitored to determine when data is available, where the frame boundaries are, etc.

-mnorman

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MCF5484 FEC and fast responses

Re: MCF5484 FEC and fast responses