topic MCF5282 FEC questions in ColdFire/68K Microcontrollers and Processors https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5282-FEC-questions/m-p/142535#M2580 <HTML><HEAD></HEAD><BODY><SPAN>Hi,</SPAN><BR /><BR /><SPAN>I am wondering if ECR[ETH_ENABLE] must be set in order to generate MII management frames, and what happens when ECR[ETH_ENABLE] is toggled on/off during communication with an attached PHY device? Also, what happens if the FEC is reset during communication with an attached PHY device?</SPAN><BR /><BR /><SPAN>One last thing, the user manual refers to an "MII_STATUS register" in one spot. What is that exactly?</SPAN><BR /><BR /><SPAN>Thanks,</SPAN><BR /><BR /><SPAN>Mike</SPAN></BODY></HTML> Sat, 08 Jul 2006 15:31:58 GMT MikeBobowik 2006-07-08T15:31:58Z MCF5282 FEC questions https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5282-FEC-questions/m-p/142535#M2580 <HTML><HEAD></HEAD><BODY><SPAN>Hi,</SPAN><BR /><BR /><SPAN>I am wondering if ECR[ETH_ENABLE] must be set in order to generate MII management frames, and what happens when ECR[ETH_ENABLE] is toggled on/off during communication with an attached PHY device? Also, what happens if the FEC is reset during communication with an attached PHY device?</SPAN><BR /><BR /><SPAN>One last thing, the user manual refers to an "MII_STATUS register" in one spot. What is that exactly?</SPAN><BR /><BR /><SPAN>Thanks,</SPAN><BR /><BR /><SPAN>Mike</SPAN></BODY></HTML> Sat, 08 Jul 2006 15:31:58 GMT https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5282-FEC-questions/m-p/142535#M2580 MikeBobowik 2006-07-08T15:31:58Z Re: MCF5282 FEC questions https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5282-FEC-questions/m-p/142536#M2581 <HTML><HEAD></HEAD><BODY>Hi again,<BR /><BR />After realising I posted this on a Friday, I decided to try and answer my own questions:<BR /><BR />As I expected, ECR[ETH_ENABLE] has no effect on the MII.<BR /><BR />A reset will completely terminate any communication with an attached PHY device. This means that if I write a routine to read and write PHY registers, it has to be aware of resets so that it doesn't hang waiting for an MII event.<BR /><BR />I would appriciate it if someone could confirm this or let me know if I have missed something.<BR /><BR />Mike</BODY></HTML> Sun, 09 Jul 2006 14:04:12 GMT https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5282-FEC-questions/m-p/142536#M2581 MikeBobowik 2006-07-09T14:04:12Z