slow /TA for MCF5234

bernd — Mon, 18 Jun 2007 19:24:25 GMT

I have slow component which should be hooked directly to the memory interface. Is there a limit how long the processor waits for a TA if external termination is selected. I would expect that everything up to 15 bus clock cycles is OK but what happens after this. For instance the external bus is correctly defined only after 250ns while with 150MHz processor clock rate -> 75 MHz bus clock rate ->15 cycles expire after 200ns. A pointer where to read would be appreciated as I did not find the information.

Re: slow /TA for MCF5234

Martin_ — Tue, 19 Jun 2007 19:38:46 GMT

Hi bernd,

External bus cycle can be terminated either externally (external /TA signal) or internally (/TA generated internally).

Chip select control register is used to set up transfer acknowledge.

CSCRn[AA] = 0
means a bus cycle is terminated externally. /TA input pin of MCF523X should be connected with /TA signal of an external device.

CSCRn[AA] = 1
CSCRn[IWS] = 0xF (15 wait states)
means /TA is asserted internally as specified by CSCRn[IWS]. An external /TA is not needed.
However, if an external /TA is connected, and external device asserts an external /TA before the wait state countdown asserts the internal /TA, the cycle is terminated.

Every external bus cycle is monitored by a bus monitor by default after reset.
The bus monitor timeout is set according to CCR[BMT] bits (65536 system clocks by default).
If a bus cycle is not terminated withing the time period defined by CCR[BMT] bits, the bus cycle is terminated by bus monitor, if enabled.

Chip select cotrol register is described in the MCF5235 Reference Manual, Chapter 16.
CCR register is described in MCF5235 Reference Manual, Chapter 9

Martin

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slow /TA for MCF5234

Re: slow /TA for MCF5234